PCF2127ATSLASH1 datasheet(39/80 Pages) NXP

39 / 80 page

PCF2127A_2

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 02 — 7 May 2010

39 of 80

NXP Semiconductors

PCF2127A

Integrated RTC, TCXO and quartz crystal

When the countdown timer flag CDTF is set, an interrupt signal on INT will be generated

provided that this mode is enabled. See Section 8.13.2 for details on how the interrupt can

be controlled.

When starting the countdown timer for the first time, only the first period will not have a

fixed duration. The amount of inaccuracy for the first timer period will depend on the

chosen source clock, see Table 38.

At the end of every countdown, the timer sets the countdown timer flag (CDTF). CDTF

may only be cleared by software. The asserted CDTF can be used to generate an

interrupt (INT). The interrupt may be generated as a pulsed signal every countdown

period or as a permanently active signal which follows the condition of CDTF. TI_TP is

used to control this mode selection. The interrupt output may be disabled with the CDTIE

bit, see Table 6.

When reading the timer, the actual countdown value is returned and not the initial value n.

Since it is not possible to freeze the countdown timer counter during read back, it is

recommended to read the register twice and check for consistent results.

8.11.5 Pre-defined timers: second and minute interrupt

PCF2127A has two pre-defined timers which are used to generate an interrupt either once

per second or once per minute. The pulse generator for the minute or second interrupt

operates from an internal 64 Hz clock. It is independent of the watchdog or countdown

timers. Each of these timers can be enabled by the bits SI (second interrupt) and MI

(minute interrupt) in register Control_1.

8.11.6 Clearing flags

The flags MSF, CDTF, AF and TSFx can be cleared by using the interface. To prevent one

flag being overwritten while clearing another, a logic AND is performed during the write

access. A flag is cleared by writing logic 0 whilst a flag is not cleared by writing logic1.

Writing logic1 will result in the flag value remaining unchanged.

Four examples are given for clearing the flags. Clearing the flags is made by a write

command:

• Bits labeled with - must be written with their previous values

• WDTF is read only and has to be written with logic 0

Repeatedly re-writing these bits has no influence on the functional behavior.

Table 38.

First period delay for timer counter

Timer source clock

Minimum timer period

Maximum timer period

4.096 kHz

n + 1

64 Hz

n + 1

1 Hz

− 1) + 1⁄

64 Hz

n + 1

⁄

64 Hz

⁄

60 Hz

− 1) + 1⁄

64 Hz

n + 1

⁄

64 Hz

Table 39.

Flag location in register Control_2

Bit

Control_2

MSF

WDTF

TSF2

CDTF

PCF2127AT/1 bảng dữ liệu(PDF) 39 Page - NXP Semiconductors

PCF2127AT/1 bảng dữ liệu(HTML) 39 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

bảng dữ liệu tải về

Link URL