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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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MMA8450QT bảng dữ liệu(PDF) 43 Page - Freescale Semiconductor, Inc |
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MMA8450QT bảng dữ liệu(HTML) 43 Page - Freescale Semiconductor, Inc |
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43 / 57 page  Sensors 43 Freescale Semiconductor MMA8450Q Appendix A Table 64. MMA8450Q Register Map Reg Name Definition Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 00 STATUS Data Status R ZYXOW ZOW YOW XOW ZYXDR ZDR YDR XDR 01 OUT_X_MSB 8-bit X Data R XD11 XD10 XD9 XD8 XD7 XD6 XD5 XD4 02 OUT_Y_MSB 8-bit Y Data R YD11 YD10 YD9 YD8 YD7 YD6 YD5 YD4 03 OUT_Z_MSB 8-bit Z Data R ZD11 ZD10 ZD9 ZD8 ZD7 ZD6 ZD5 ZD4 04 STATUS Data Status R ZYXOW ZOW YOW XOW ZYXDR ZDR YDR XDR 05 OUT_X_LSB 12-bit X Data R 0 0 0 0 XD3 XD2 XD1 XD0 06 OUT_X_MSB 12-bit X Data R XD11 XD10 XD9 XD8 XD7 XD6 XD5 XD4 07 OUT_Y_LSB 12-bit Y Data R 0 0 0 0 YD3 YD2 YD1 YD0 08 OUT_Y_MSB 12-bit Y Data R YD11 YD10 YD9 YD8 YD7 YD6 YD5 YD4 09 OUT_Z_LSB 12-bit Z Data R 0 0 0 0 ZD3 ZD2 ZD1 ZD0 0A OUT_Z_MSB 12-bit Z Data R ZD11 ZD10 ZD9 ZD8 ZD7 ZD6 ZD5 ZD4 0B STATUS Data Status R ZYXOW ZOW YOW XOW ZYXDR ZDR YDR XDR 0C OUT_X_DELTA 8-bit Transient X Data R XD7 XD6 XD5 XD4 XD3 XD2 XD1 XD0 0D OUT_Y_DELTA 8-bit Transient Y Data R YD7 YD6 YD5 YD4 YD3 YD2 YD1 YD0 0E OUT_Z_DELTA 8-bit Transient Z Data R ZD7 ZD6 ZD5 ZD4 ZD3 ZD2 ZD1 ZD0 0F WHO_AM_I ID Register R — — — — — — — — 10 F_STATUS FIFO Status R F_OVF F_WMRK_FLAG F_CNT5 F_CNT4 F_CNT3 F_CNT2 F_CNT1 F_CNT0 11 F_8DATA 8-bit FIFO Data R XD11 XD10 XD9 XD8 XD7 XD6 XD5 XD4 12 F_12DATA 12-bit FIFO Data R 0 0 0 0 XD3 XD2 XD1 XD0 13 F_SETUP FIFO Setup R/W F_MODE1 F_MODE0 F_WMRK5 F_WMRK4 F_WMRK3 F_WMRK2 F_WMRK1 F_WMRK0 14 SYSMOD System Mode R PERR FGERR 0 0 0 0 SYSMOD1 SYSMOD0 15 INT_SOURCE Interrupt Status R SRC_ASLP SRC_FIFO SRC_TRANS SRC_LNDPRT SRC_PULSE SRC_FF_MT_1 SRC_FF_MT_2 SRC_DRDY 16 XYZ_DATA_CFG Data Config. R/W FDE 0 0 0 — ZDEFE YDEFE XDEFE 17 HP_FILTER_CUTOFF HP Filter Setting R/W 0 0 0 0 0 0 SEL1 SEL0 18 PL_STATUS PL Status R NEWLP LO - LAPO[2] LAPO[1] LAPO[0] BAFRO[1] BAFRO[0] 19 PL_PRE_STATUS Previous PL Status R - LO - LAPO[2] LAPO[1] LAPO[0] BAFRO[1] BAFRO[0] 1A PL_CFG PL Configuration R/W DBCNTM PL_EN - - - GOFF[2] GOFF[1] GOFF[0] 1B PL_COUNT PL Debounce R/W DBNCE[7] DBNCE[6] DBNCE[5] DBNCE[4] DBNCE[3] DBNCE [2] DBNCE [1] DBNCE [0] 1C PL_BF_ZCOMP PL Back/Front and Z Compensation R/W BKFR[1] BKFR[0] - - - ZLOCK[2] ZLOCK[1] ZLOCK[0] 1D PL_P_L_THS_REG1 Portrait-to-Landscape Threshold Setting 1 R/W P_L_THS[7] P_L_THS[6] P_L_THS[5] P_L_THS[4] P_L_THS[3] P_L_THS[2] P_L_THS[1] P_L_THS[0] 1E PL_P_L_THS_REG2 Portrait-to-Landscape Threshold Setting 2 R/W P_L_THS[7] P_L_THS[6] P_L_THS[5] P_L_THS[4] P_L_THS[3] P_L_THS[2] P_L_THS[1] P_L_THS[0] 1F PL_P_L_THS_REG3 Portrait-to-Landscape Threshold Setting 3 R/W P_L_THS[7] P_L_THS[6] P_L_THS[5] P_L_THS[4] P_L_THS[3] P_L_THS[2] P_L_THS[1] P_L_THS[0] 20 PL_L_P_THS_REG1 Landscape-to-Portrait Threshold Setting 1 R/W L_P_THS[7] L_P_THS[6] L_P_THS[5] L_P_THS[4] L_P_THS[3] L_P_THS[2] L_P_THS[1] L_P_THS[0] 21 PL_L_P_THS_REG2 Landscape-to-Portrait Threshold Setting21 R/W L_P_THS[7] L_P_THS[6] L_P_THS[5] L_P_THS[4] L_P_THS[3] L_P_THS[2] L_P_THS[1] L_P_THS[0] 22 PL_L_P_THS_REG3 Landscape-to-Portrait Threshold Setting 3 R/W L_P_THS[7] L_P_THS[6] L_P_THS[5] L_P_THS[4] L_P_THS[3] L_P_THS[2] L_P_THS[1] L_P_THS[0] 23 FF_MT_CFG_1 FF/Motion Config. 1 R/W ELE OAE ZHEFE ZLEFE YHEFE YLEFE XHEFE XLEFE 24 FF_MT_SRC_1 FF/Motion Source 1 R — EA ZHE ZLE YHE YLE XHE XLE 25 FF_MT_THS_1 FF/Motion Threshold 1 R/W DBCNTM THS6 THS5 THS4 THS3 THS2 THS1 THS0 26 FF_MT_COUNT_1 FF/Motion Debounce 1 R/W D7 D6 D5 D4 D3 D2 D1 D0 27 FF_MT_CFG_2 FF/Motion Config. 2 R/W ELE OAE ZHEFE ZLEFE YHEFE YLEFE XHEFE XLEFE 28 FF_MT_SRC_2 FF/Motion Source 2 R — EA ZHE ZLE YHE YLE XHE XLE |
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