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MMA8450QT bảng dữ liệu(PDF) 27 Page - Freescale Semiconductor, Inc

tên linh kiện MMA8450QT
Giải thích chi tiết về linh kiện  3-Axis, 8-bit/12-bit Digital Accelerometer
PDF  57 Pages
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nhà sản xuất  FREESCALE [Freescale Semiconductor, Inc]
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MMA8450QT bảng dữ liệu(HTML) 27 Page - Freescale Semiconductor, Inc

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Sensors
27
Freescale Semiconductor
MMA8450Q
0x16: XYZ_DATA_CFG Sensor Data Configuration Register
The XYZ_DATA_CFG register configures the 3-axis acceleration data and event flag generator based on the ODR.
0x17: HP_FILTER_CUTOFF High Pass Filter Register
This register sets the high-pass filter cut-off frequency for the detection of instantaneous acceleration. The output of this filter
is indicated by the OUT_X_DELTA, OUT_Y_DELTA, and OUT_Z_DELTA registers. The filter cut-off options change based on the
data rate selected as shown in Table 19. For details of implementation on the high pass filter, refer to Freescale application note
AN3918.
6.3
Portrait/ Landscape Embedded Function Registers
For more details on the meaning of the different user configurable settings and for example code refer to Freescale application
note AN3915.
0x18: PL_STATUS Portrait/Landscape Status Register
This status register can be read to get updated information on any change in orientation by reading Bit 7, or on the specifics
of the orientation by reading Bit0 to Bit 4. For further understanding of Portrait Up, Portrait Down, Landscape Left, Landscape
Right, Back and Front please refer to Figure 9
SRC_DRDY
Data Ready interrupt bit status
Logic ‘1’ indicates that the X,Y,Z data ready interrupt is active indicating the presence of new data and/or data overrun.
Otherwise if it is a logic ‘0’ the X,Y,Z interrupt is not active.
This bit is asserted when the ZYXOW and/or ZYXDR is set and the interrupt has been enabled.
This bit is cleared by reading the STATUS and X, Y, or Z register.
0x16 XYZ_DATA_CFG: Sensor Data Configuration Register (Read/Write)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
FDE
0
0
0
0
ZDEFE
YDEFE
XDEFE
Table 18. XYZ_DATA_CFG Description
FDE
FIFO Data Output Register Driver Enable. Default value: 0.
0: The sample data output registers store the current X, Y, & Z sample data;
1: The sample data output registers point to the previously stored X, Y, & Z samples data in the FIFO buffer.
ZDEFE
Data Event Flag Enable on new Z-axis data. Default value: 0
0: Event detection disabled; 1: Raise event flag on new Z-axis data
YDEFE
Data Event Flag Enable on new Y-axis data. Default value: 0
0: Event detection disabled; 1: Raise event flag on new Y-axis data
XDEFE
Data Event Flag Enable on new X-axis data. Default value: 0
0: Event detection disabled; 1: Raise event flag on new X-axis data
0x17 HP_FILTER_CUTOFF: High Pass Filter Register (Read/Write)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
SEL1
SEL0
Table 19. HP_FILTER_CUTOFF Setting Options
SEL1
SEL0
Fc (Hz) @
ODR = 400 Hz
Fc (Hz) @
ODR = 200 Hz
Fc (Hz) @
ODR = 100 Hz
Fc (Hz) @
ODR = 50 Hz
Fc (Hz) @
ODR = 12.5 Hz
Fc (Hz) @
ODR = 1.563 Hz
0
0
4
2
1
0.5
0.125
0.01
0
1
2
1
0.5
0.25
0.063
0.007
1
0
1
0.5
0.25
0.125
0.031
0.004
1
1
0.5
0.25
0.125
0.062
0.016
0.002
0x18 PL_STATUS Register (Read Only)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
NEWLP
LO
—
LAPO[2]
LAPO[1]
LAPO[0]
BAFRO[1]
BAFRO[0]
Table 17. INT_SOURCE Description



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