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MMA8450Q

0x15: INT_SOURCE System Interrupt Status Register

In the interrupt source register the status of the various embedded features can be determined.The bits that are set (logic ‘1’)

indicate which function has asserted an interrupt and conversely the bits that are cleared (logic ‘0’) indicate which function has

not asserted or has de-asserted an interrupt. The interrupts are rising edge sensitive. The bits are set by a low to high transition

and are cleared by reading the appropriate interrupt source register.

0x15 INT_SOURCE: System Interrupt Status Register (Read Only)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

SRC_ASLP

SRC_FIFO

SRC_TRANS

SRC_LNDPRT

SRC_PULSE

SRC_FF_MT_1 SRC_FF_MT_2

SRC_DRDY

Table 17. INT_SOURCE Description

INT_SOURCE

Description

SRC_ASLP

Auto-Sleep/Wake interrupt status bit

Logic ‘1’ indicates that an interrupt event that can cause a “Wake-to-Sleep” or “Sleep-to-Wake” system mode transition

has occurred.

Logic ‘0’ indicates that no “Wake-to-Sleep” or “Sleep-to-Wake” system mode transition interrupt event has occurred.

“Wake-to-Sleep” transition occurs when no interrupt occurs for a time period that exceeds the user specified limit

(ASLP_COUNT). This causes the system to transition to a user specified low ODR setting.

“Sleep-to-Wake” transition occurs when the user specified interrupt event has woken the system; thus causing the

system to transition to a user specified high ODR setting.

Reading the SYSMOD register clears the SRC_ASLP bit.

SRC_FIFO

FIFO interrupt status bit

Logic ‘1’ indicates that a FIFO interrupt event such as an overflow event or watermark has occurred. Logic ‘0’ indicates

that no FIFO interrupt event has occurred.

FIFO interrupt event generators: FIFO Overflow, or (Watermark: F_CNT = F_WMRK) and the interrupt has been

enabled.

This bit is cleared by reading the F_STATUS register.

SRC_TRANS

Transient interrupt status bit

Logic ‘1’ indicates that an acceleration transient value greater than user specified threshold has occurred. Logic ‘0’

indicates that no transient event has occurred.

This bit is asserted whenever “EA” bit in the TRANS_SRC is asserted and the interrupt has been enabled.

This bit is cleared by reading the TRANS_SRC register.

SRC_LNDPRT

Landscape/Portrait Orientation interrupt status bit

Logic ‘1’ indicates that an interrupt was generated due to a change in the device orientation status. Logic ‘0’ indicates

that no change in orientation status was detected.

This bit is asserted whenever “NEWLP” bit in the PL_STATUS is asserted and the interrupt has been enabled.

This bit is cleared by reading the PL_STATUS register.

SRC_PULSE

Pulse interrupt status bit

Logic ‘1’ indicates that an interrupt was generated due to single and/or double pulse event. Logic ‘0’ indicates that no

pulse event was detected.

This bit is asserted whenever “EA” bit in the PULSE_SRC is asserted and the interrupt has been enabled.

This bit is cleared by reading the PULSE_SRC register.

SRC_FF_MT_1

Freefall/Motion1 interrupt status bit

Logic ‘1’ indicates that the Freefall/Motion1 function interrupt is active.

Logic ‘0’ indicates that no Freefall or Motion event was detected.

This bit is asserted whenever “EA” bit in the FF_MT_SRC_1 register is asserted and the FF_MT interrupt has been

enabled.

This bit is cleared by reading the FF_MT_SRC_1 register.

SRC_FF_MT_2

Freefall/Motion2 interrupt status bit

Logic ‘1’ indicates that the Freefall/Motion2 function interrupt is active.

Logic ‘0’ indicates that no Freefall or Motion event was detected.

This bit is asserted whenever “EA” bit in the FF_MT_SRC_2 register is asserted and the FF_MT interrupt has been

enabled.

This bit is cleared by reading the FF_MT_SRC_2 register.

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