MMA8450QT datasheet(38/57 Pages) FREESCALE

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MMA8450Q

0x35: PULSE_LTCY Pulse Latency Timer Register

The bits Ltcy7 through Ltcy0 define the time interval that starts after the first pulse detection. During this time interval, all pulses

are ignored. Note: This timer must be set for single pulse and for double pulse.

The minimum time step for the pulse latency is defined in Table 49. The maximum time is the time step at the ODR and Power

Mode multiplied by 255. Notice that the time step is twice the duration if the device is operating in Low Power mode, as shown

below.

0x36: PULSE_WIND Second Pulse Time Window Register

The bits Wind7 through Wind0 define the maximum interval of time that can elapse after the end of the latency interval in which

the start of the second pulse event must be detected provided the device has been configured for double pulse detection. The

detected second pulse width must be shorter than the time limit constraints specified by the PULSE_TMLT register, but the end

of the double pulse need not finish within the time specified by the PULSE_WIND register.

The minimum time step for the pulse window is defined in Table 50. The maximum time is the time step at the ODR and Power

Mode multiplied by 255.

6.7

Auto-Sleep Registers

For additional information on how to configure the device for the Auto-Sleep/Wake feature, refer to AN3921.

0x37: ASLP_COUNT Auto-Sleep Inactivity Timer Register

The ASLP_COUNT register sets the minimum time period of inactivity required to change current ODR value from the value

specified in the DR[2:0] to ASLP_RATE (Reg 0x38) value provided the SLPE bit is set to a logic ‘1’ in the CTRL_REG2 register.

0x35 PULSE_LTCY Register (Read/Write)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Ltcy7

Ltcy6

Ltcy5

Ltcy4

Ltcy3

Ltcy2

Ltcy1

Ltcy0

Table 49. Time Step for PULSE Latency at ODR and Power Mode

Output Data Rate (Hz)

Step at Normal Mode

Step at Low Power Mode

400

1.25 ms

2.5 ms

200

2.5 ms

5.0 ms

100

5.0 ms

20 ms

10 ms

20 ms

12.5

10 ms

20 ms

1.56

10 ms

20 ms

0x36 PULSE_WIND Register (Read/Write)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Wind7

Wind6

Wind5

Wind4

Wind3

Wind2

Wind1

Wind0

Table 50. Time Step for PULSE Detection Window at ODR and Power Mode

Output Data Rate (Hz)

Step at Normal Mode

Step at Low Power Mode

400

1.25 ms

2.5 ms

200

2.5 ms

5.0 ms

100

5.0 ms

20 ms

10 ms

20 ms

12.5

10 ms

20 ms

1.56

10 ms

20 ms

0x37 ASLP_COUNT Register (Read/Write)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Table 51. ASLP_COUNT Description

D[7-0]

Duration value. Default value: 0000 0000

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