MMA8450QT datasheet(42/57 Pages) FREESCALE

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Sensors

Freescale Semiconductor

MMA8450Q

The corresponding functional block interrupt enable bit allows the functional block to route its event detection flags to the

system’s interrupt controller. The interrupt controller routes the enabled functional block interrupt to the INT1 or INT2 pin.

0x3C: CTRL_REG5 Interrupt Configuration Register

The system’s interrupt controller shown in Figure 10 uses the corresponding bit field in the CTRL_REG5 register to determine

the routing table for the INT1 and INT2 interrupt pins. If the bit value is logic ‘0’ the functional block’s interrupt is routed to INT2,

and if the bit value is logic ‘1’ then the interrupt is routed to INT1. One or more functions can assert an interrupt pin; therefore a

host application responding to an interrupt should read the INT_SOURCE (0x15) register to determine the appropriate sources

of the interrupt.

6.8

User Offset Correction Registers

For more information on how to calibrate the 0g Offset refer to AN3916 Offset Calibration Using the MMA8450Q. The 2’s

complement offset correction registers values are used to realign the zero g position of the X, Y, and Z-axis after device board

mount. The resolution of the offset registers is 3.906 mg per LSB. The 2’s complement 8-bit value would result in an offset

compensation range ±0.5g.

0x3D: OFF_X Offset Correction X Register

0x3E: OFF_Y Offset Correction Y Register

0x3F: OFF_Z Offset Correction Z Register

0x3C CTRL_REG5 Register (Read/Write)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INT_CFG_ASLP

INT_CFG_FIFO

INT_CFG_TRANS INT_CFG_LNDPRT INT_CFG_PULSE INT_CFG_FF_MT_1INT_CFG_FF_MT_2 INT_CFG_DRDY

Table 60. Interrupt Configuration Register Description

Interrupt Configuration

Description

INT_CFG_ASLP