MMA8450QT datasheet(40/57 Pages) FREESCALE

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Sensors

Freescale Semiconductor

MMA8450Q

FS[1:0] bits select between standby mode and active mode. The default value is 00 for standby mode.

0x39: CTRL_REG2 System Control 2 Register

ST bit activates the Self-Test function. When ST is set to one, an output change will occur to the device outputs (refer to Table 2

and Table 3) thus allowing host application to check the functionality of the entire signal chain.

BOOT bit is used to activate the software reset. The Boot mechanism can be enabled in STANDBY and ACTIVE mode.

When the Boot bit is enabled the Boot mechanism resets all functional block registers and loads the respective internal

registers with default NVM values.

The system will automatically transition to standby mode if not already in standby mode before the software reset (re-BOOT

process) can occur.

Note: The I2C communication system is reset to avoid accidental corrupted data access.

0x3A: CTRL_REG3 Interrupt Control Register

100 Hz

10 ms

50 Hz

20 ms

12.5 Hz

80 ms

1.563 Hz

640 ms

Table 56. Full Scale Selection

FS1

FS0

Mode

g Range

Standby

—

Active

±2g

Active

±4g

Active

±8g

0x39 CTRL_REG2 Register (Read/Write)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

BOOT

SLPE

MODS

Table 57. CTRL_REG2 Description

Self-Test Enable. Default value: 0

0: Self-Test disabled; 1: Self-Test enabled

BOOT

Reboot device content (Software Reset). Default value: 0

0: device reboot disabled; 1: device reboot enabled.

SLPE(1)

1. When SLPE = 1, the transitioning between sleep mode and wake mode results in a FIFO flush and a reset of internal functional block counters. All functional block

status information are preserve except otherwise stated. See Table 58 for more information about the FIFO_GATE bit in CTRL_REG3 register.

Auto-Sleep enable. Default value: 0

0: Auto-Sleep is not enabled;

1: Auto-Sleep is enabled.

MODS

Low power mode / Normal mode selection. Default value: 0

0: normal mode; 1: low power mode.

0x3A CTRL_REG3 Register (Read/Write)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

FIFO_GATE

WAKE_TRANS

WAKE_LNDPRT

WAKE_PULSE WAKE_FF_MT_1 WAKE_FF_MT_2

IPOL

PP_OD

Table 55. System Output Data Rate Selection

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