MMA8450QT datasheet(23/57 Pages) FREESCALE

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MMA8450Q

The sample data output registers store the current sample data if the FIFO data output register driver is disabled, but if the

FIFO data output register driver is enabled,12 the sample data output registers point to the head of the FIFO buffer which contains

the previous 32 X, Y, and Z data samples. This applies for the 8-bit data and the 12-bit data.

When the FDE bit is set to logic 1, the F_8DATA (0x11) FIFO root data pointer shares the same address location as the

OUT_X_MSB register (0x01); therefore all 8-bit accesses of the FIFO buffer data must use the I2C address 0x01. The F_12DATA

(0x12) FIFO root data pointer shares the same address location as the OUT_X_LSB register (0x05); therefore all 12-bit accesses

of the FIFO buffer data must use the I2C address 0x05. All reads to register addresses 0x02, 0x03, 0x06, 0x07, 0x08, 0x09, and

0x0A returns a value of 0x00.

0x0C - 0x0E: OUT_X_DELTA, OUT_Y_DELTA, OUT_Z_DELTA AC Data Registers

X, Y, and Z-axis 8-bit high pass filtered output data is expressed as 2's complement numbers. The data is obtained from the

output of the user definable high pass filter. The data cuts out the low frequency data, which is useful in that the offset data is

removed. The value of the high pass filter cut off frequency is set in Register 0x17.

Note: The OUT_X_DELTA, OUT_Y_DELTA, OUT_Z_DELTA registers store the high pass filtered “delta data” information regardless of the state

of the FIFO data output register driver bit. Register 0x0B always reflects the status of the delta data.

0x0F: WHO_AM_I Device ID Register

This register contains the device identifier which for MMA8450Q is set to 0xC6 by default. The value is factory programmed

by a byte of NVM. A custom alternate value can be set by customer request.

6.2

32 Sample FIFO

The following registers are used to configure the FIFO. The following are the FIFO registers for the MMA8450Q. For more

information on the FIFO please refer to AN3920.

0x10: F_STATUS FIFO Status Register

The FIFO Status Register is used to retrieve information about the FIFO. This register has a flag for the overflow and

watermark. It also has a counter that can be read to obtain the number of samples stored in the buffer.

The F_OVF and F_WMRK_FLAG flags remain asserted while the event source is still active, but the user can clear the FIFO

interrupt bit flag in the interrupt source register (INT_SOURCE) by reading the F_STATUS register.

Therefore the F_OVF bit flag will remain asserted while the FIFO has overflowed and the F_WMRK_FLAG bit flag will remain

asserted while the F_CNT value is greater than the F_WMRK value.

0x0C OUT_X_DELTA: AC X 8-Bit Data Register (Read Only)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

XD7

XD6

XD5

XD4

XD3

XD2

XD1

XD0

0x0D OUT_Y_DELTA: AC Y 8-Bit Data Register (Read Only)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

YD7

YD6

YD5

YD4

YD3

YD2

YD1

YD0

0x0E OUT_Z_DELTA: AC Z 8-Bit Data Register (Read Only)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ZD7ZD6

ZD5ZD4

ZD3ZD2

ZD1ZD0

0x0F WHO_AM_I: Device ID Register (Read Only)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

1100011

0x10 F_STATUS: FIFO STATUS Register (Read Only)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

F_OVF

F_WMRK_FLAG

F_CNT5

F_CNT4

F_CNT3

F_CNT2

F_CNT1

F_CNT0

Table 13. FIFO Flag Event Description

F_OVF

F_WMRK_FLAG

Event Description

—

No FIFO overflow events detected.

—

FIFO event detected; FIFO has overflowed.

—

No FIFO watermark events detected.

—

FIFO event detected; FIFO sample count is greater than watermark value.

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