MMA8450QT datasheet(25/57 Pages) FREESCALE

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Sensors

Freescale Semiconductor

MMA8450Q

A FIFO sample count exceeding the watermark event does not stop the FIFO from accepting new data. The FIFO update rate

is dictated by the selected system ODR. In active mode the ODR is set by the DR register in the CTRL_REG1 register and when

Auto-Sleep is active the ODR is set by the ASLP_RATE field in the CTRL_REG1 register.

When a byte is read from the FIFO buffer the oldest sample data in the FIFO buffer is returned and also deleted from the front

of the FIFO buffer, while the FIFO sample count is decremented by one. It is assumed that the host application shall use the I2C

multi-read transaction to empty the FIFO.

The FIFO mode can be changed while in the active state. The mode must first be disabled F_MODE = 00 then the Mode can

be changed.

0x14: SYSMOD System Mode Register

The system mode register indicates the current device operating mode. Applications using the Auto-Sleep/Auto-Wake

mechanism should use this register to synchronize the application with the device operating mode transitions. The system mode

The FIFO Gate is set in Register 0x3A for the device configured for Auto-Wake/Sleep mode to allow the buffer to preserve the

data without automatically flushing. If the FIFO buffer is not emptied before the arrival of the next sample, then the FGERR bit in

buffer clears the FGERR bit.

Table 15. F_SETUP Description

BITS

Description

F_MODE[1:0](1)(2)(3)

FIFO buffer overflow mode. Default value 0.

00: FIFO is disabled.

01: FIFO contains the most recent samples when overflowed (circular buffer). Oldest sample is discarded to

be replaced by new sample.

10: FIFO stops accepting new samples when overflowed.

11: Not Used.

The FIFO is flushed whenever the FIFO is disabled, during an automatic ODR change (Auto-Wake/Sleep), or

transitioning from “STANDBY” mode to “ACTIVE” mode.

Disabling the FIFO (F_MODE = 00) resets the F_OVF, F_WMRK_FLAG, F_CNT to zero.

A FIFO overflow event (i.e., F_CNT = 32) will assert the F_OVF flag and a FIFO sample count equal to the

sample count watermark (i.e., F_WMRK) asserts the F_WMRK_FLAG event flag.

F_WMRK[5:0](2)

FIFO Event Sample Count Watermark. Default value 00_0000.

These bits set the number of FIFO samples required to trigger a watermark interrupt. A FIFO watermark event

flag (F_WMK_FLAG) is raised when FIFO sample count F_CNT[5:0] value is equal to the F_ WMRK[5:0]

watermark.

Setting the F_WMRK[5:0] to 00_0000 will disable the FIFO watermark event flag generation.

1. Bit field can be written in ACTIVE mode.

2. Bit field can be written in STANDBY mode.

3. The FIFO mode (F_MODE) cannot be switched between the two operational modes (01and 10) in Active Mode.

0x14 SYSMOD: System Mode Register (Read Only)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PERR

FGERR

0000

SYSMOD1

SYSMOD0

Table 16. SYSMOD Description

PERR

NVM Parity Error Flag Bit. Default Value: 0.

0: No NVM parity error was detected.

1: NVM parity error detected.

FGERR

FIFO Gate Error. Default value: 0.

0: No FIFO Gate Error detected.

1: FIFO Gate Error was detected.

SYSMOD

System Mode. Default value: 00.

00: Standby mode

01: Wake mode

10: Sleep mode

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