STM32W108HB datasheet(147/179 Pages) STMICROELECTRONICS

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STM32W108CB, STM32W108HB

Interrupts

Doc ID 16252 Rev 2

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Figure 47.

Peripheral interrupts block diagram

The description of each peripheral's interrupt configuration and flag registers can be found

in the chapters of this datasheet describing each peripheral.

Given a peripheral, 'periph', the Event Manager registers (INT_periphCFG and

INT_periphFLAG) follow the form:

●

INT_periphCFG enables and disables second-level interrupts. Writing 1 to a bit in the

INT_periphCFG register enables the second-level interrupt. Writing 0 to a bit in the

INT_periphCFG register disables it. The INT_periphCFG register behaves like a mask,

and is responsible for allowing the INT_periphFLAG bits to propagate into the top level

NVIC interrupts.

●

INT_periphFLAG indicates second-level interrupts that have occurred. Writing 1 to a bit

in a INT_periphFLAG register clears the second-level interrupt. Writing 0 to any bit in

the INT_periphFLAG register is ineffective. The INT_periphFLAG register is always

active and may be set or cleared at any time, meaning if any second-level interrupt

occurs, then the corresponding bit in the INT_periphFLAG register is set regardless of

the state of INT_periphCFG.

If a bit in the INT_periphCFG register is set after the corresponding bit in the

INT_periphFLAG register is set then the second-level interrupt propagates into the top level

interrupts. The interrupt flags (signals) from the second-level interrupts into the top-level

interrupts are level-sensitive. If a top-level NVIC interrupt is driven by a second-level EM

interrupt, then the top-level NVIC interrupt cannot be cleared until all second-level EM

interrupts are cleared.

The INT_periphFLAG register bits are designed to remain set if the second-level interrupt

event re-occurs at the same moment as the INT_periphFLAG register bit is being cleared.

This ensures the re-occurring second-level interrupt event is not missed.

If another enabled second-level interrupt event of the same type occurs before the first

interrupt event is cleared, the second interrupt event is lost because no counting or queuing

is used. However, this condition is detected and stored in the top-level INT_MISS register to

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