STM32W108HB datasheet(52/179 Pages) STMICROELECTRONICS

52 / 179 page

General-purpose input/outputs

STM32W108CB, STM32W108HB

52/179

Doc ID 16252 Rev 2

External interrupts have individual triggering and filtering options selected using the

registers GPIO_INTCFGA, GPIO_INTCFGB, GPIO_INTCFGC, and GPIO_INTCFGD. The

bit field GPIO_INTMOD of the GPIO_INTCFGx register enables IRQx's second level

interrupt and selects the triggering mode: 0 is disabled; 1 for rising edge; 2 for falling edge; 3

for both edges; 4 for active high level; 5 for active low level. The minimum width needed to

latch an unfiltered external interrupt in both level- and edge-triggered mode is 80 ns. With

the digital filter enabled (the GPIO_INTFILT bit in the GPIO_INTCFGx register is set), the

minimum width needed is 450 ns.

The register INT_GPIOFLAG is the second-level interrupt flag register that indicates

pending external interrupts. Writing 1 to a bit in the INT_GPIOFLAG register clears the flag

while writing 0 has no effect. If the interrupt is level-triggered, the flag bit is set again

immediately after being cleared if its input is still in the active state.

Two of the four external interrupts, IRQA and IRQB, have fixed pin assignments. The other

two external interrupts, IRQC and IRQD, can use any GPIO pin. The GPIO_IRQCSEL and

GPIO_IRQDSEL registers specify the GPIO pins assigned to IRQC and IRQD, respectively.

Table 7 shows how the GPIO_IRQCSEL and GPIO_IRQDSEL register values select the

GPIO pin used for the external interrupt.

In some cases, it may be useful to assign IRQC or IRQD to an input also in use by a

peripheral, for example to generate an interrupt from the slave select signal (nSSEL) in an

SPI slave mode interface.

Refer to Section 10: Interrupts on page 143 for further information regarding the

STM32W108 interrupt system.

6.3

Debug control and status

Two GPIO registers are largely concerned with debugger functions. GPIO_DBGCFG can

disable debugger operation, but has other miscellaneous control bits as well.

GPIO_DBGSTAT, a read-only register, returns status related to debugger activity

(GPIO_FORCEDBG and GPIO_SWEN), as well a flag (GPIO_BOOTMODE) indicating

whether nBOOTMODE was asserted at the last power-on or NRST-based reset.

Table 7.

IRQC/D GPIO selection

GPIO_IRQxSEL

GPIO

GPIO_IRQxSEL

GPIO

GPIO_IRQxSEL

GPIO

PA0

PB0

PC0

PA1

PB1

PC1

PA2

PB2

PC2

PA3

PB3

PC3

PA4

PB4

PC4

PA5

PB5

PC5

PA6

PB6

PC6

PA7

PB7

PC7

STM32W108HB bảng dữ liệu(PDF) 52 Page - STMicroelectronics

STM32W108HB bảng dữ liệu(HTML) 52 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL