STM32W108HB datasheet(44/179 Pages) STMICROELECTRONICS

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System modules

STM32W108CB, STM32W108HB

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Doc ID 16252 Rev 2

5.5.2

Basic sleep modes

The power management state diagram in Figure 7 shows the basic operation of the power

management controller.

Figure 7.

Power management state diagram

In normal operation an application may request one of two low power modes through

program execution:

●

Idle Sleep is achieved by executing a WFI instruction whilst the SLEEPDEEP bit in the

Cortex System Control register (SCS_SCR) is clear. This puts the CPU into an idle

state where execution is suspended until an interrupt occurs. This is indicated by the

state at the bottom of the diagram. Power is maintained to the core logic of the

STM32W108 during the Idle Sleeping state.

●

Deep sleep is achieved by executing a WFI instruction with the SLEEPDEEP bit in

SCS_SCR set. This triggers the state transitions around the main loop of the diagram,

resulting in powering down the STM32W108's core logic, and leaving only the always-

on domain powered. Wake up is triggered when one of the pre-determined events

occurs.

If a deep sleep is requested the STM32W108 first enters a pre-deep sleep state. This state

prevents any section of the chip from being powered off or reset until the SWJ goes idle (by

clearing CSYSPWRUPREQ). This pre-deep sleep state ensures debug operations are not

interrupted.

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