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STM32W108HB bảng dữ liệu(PDF) 41 Page - STMicroelectronics

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STM32W108CB, STM32W108HB
System modules
Doc ID 16252 Rev 2
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5.3.6
Clock switching registers
XTAL or OSCHF main clock select register (OSC24M_CTRL)
Address offset: 0x4000 401C
Reset value: 0x0000 0000
CPU clock source select register (CPU_CLK_SEL)
Address offset: 0x4000 4020
Reset value: 0x0000 0000
Table 3.
System clock modes
OSC24M_SEL CPU_CLK_SEL
SCLK
PCLK
FCLK
Flash
Program/
Erase Inactive
Flash
Program/
Erase Active
0 (OSCHF)
0 (Normal CPU)
12 MHz
6 MHz
6 MHz
12 MHz
0 (OSCHF)
1 (Fast CPU)
12 MHz
6 MHz
12 MHz
12 MHz
1 (OSC24M)
0 (Normal CPU)
24 MHz
12 MHz
12 MHz
12 MHz
1 (OSC24M)
1 (Fast CPU)
24 MHz
12 MHz
24 MHz
12 MHz
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
rrr
rrr
r
r
r
r
r
r
r
r
r
r
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
OSC24
M_EN
OSC24
M_SEL
rrr
rrr
r
r
r
r
r
r
r
r
rws
rws
1 OSC24M_EN: When set to ‘1’, 24 MHz crystal oscillator is main clock.
0 OSC24M_SEL: When set to ‘0’, OSCHF is selected. When set to ‘1’, XTAL is selected.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
rrr
rrr
r
r
r
r
r
r
r
r
r
r
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CPU_C
LK_SEL
rrr
rrr
r
r
r
r
r
r
r
r
rws
rws
0 CPU_CLK_SEL: When set to ‘0’, 12-MHz CPU clock is selected. When set to ‘1’, 24-MHz CPU
clock is selected. Note that the clock selection also determines if RAM controller is running at
the same speed as the HCLK (CPU_CLK_SEL = ‘1’) or double speed of HCLK (CPU_CLK_SEL
= ‘0’).



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