STM32W108HB datasheet(85/179 Pages) STMICROELECTRONICS

tên linh kiện	STM32W108HB

Giải thích chi tiết về linh kiện	High-performance, IEEE 802.15.4 wireless system-on-chip

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STM32W108CB, STM32W108HB

General-purpose timers

Doc ID 16252 Rev 2

85/179

Figure 14.

Counter timing diagram, update event when TIM_ARBE = 0 (TIMx_ARR

not buffered)

Figure 15.

Counter timing diagram, update event when TIM_ARBE = 1 (TIMx_ARR

buffered)

Down-counting mode

In down-counting mode, the counter counts from the auto-reload value (contents of the

TIMx_ARR register) down to 0, then restarts from the auto-reload value and generates a

counter underflow event.

An update event can be generated at each counter underflow, by setting the TIM_UG bit in

the TIMx_EGR register, or by using the slave mode controller). Software can disable the

update event by setting the TIM_UDIS bit in the TIMx_CR1 register, to avoid updating the

shadow registers while writing new values in the buffer registers. No update event occurs

until the TIM_UDIS bit is written to 0. However, the counter restarts from the current auto-

reload value, whereas the prescalar's counter restarts from 0, but the prescale rate doesn't

change.

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