STM32W108HB datasheet(95/179 Pages) STMICROELECTRONICS

95 / 179 page

STM32W108CB, STM32W108HB

General-purpose timers

Doc ID 16252 Rev 2

95/179

Figure 29.

PWM input mode timing

8.1.7

Forced output mode

In output mode (CCyS bits = 00 in the TIMx_CCMR1 register), software can force each

output compare signal (OCyREF and then OCy) to an active or inactive level independently

of any comparison between the output compare register and the counter.

To force an output compare signal (OCyREF/OCy) to its active level, write 101 in the

TIM_OCyM bits in the corresponding TIMx_CCMR1 register. OCyREF is forced high

(OCyREF is always active high) and OCy gets the opposite value to the TIM_CCyP polarity

bit. For example, TIM_CCyP = 0 defines OCy as active high, so when OCyREF is active,

OCy is also set to a high level.

The OCyREF signal can be forced low by writing the TIM_OCyM bits to 100 in the

TIMx_CCMR1 register.

The comparison between the TIMx_CCRy shadow register and the counter is still performed

and allows the INT_TIMxCCRyIF flag to be set. Interrupt requests can be sent accordingly.

This is described in Section 8.1.8: Output compare mode on page 95.

8.1.8

Output compare mode

This mode is used to control an output waveform or to indicate when a period of time has

elapsed.

When a match is found between the capture/compare register and the counter, the output

compare function:

●

Assigns the corresponding output pin to a programmable value defined by the output

compare mode (the TIM_OCyM bits in the TIMx_CCMR1 register) and the output

polarity (the TIM_CCyP bit in the TIMx_CCER register). The output can remain

unchanged (TIM_OCyM = 000), be set active (TIM_OCyM = 001), be set inactive

(TIM_OCyM = 010), or can toggle (TIM_OCyM = 011) on the match.

●

Sets a flag in the interrupt flag register (the INT_TIMCCyIF bit in the INT_TIMxFLAG

●

Generates an interrupt if the corresponding interrupt mask is set (the TIM_CCyIF bit in

the INT_TIMxCFG register).

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