STM32W108HB datasheet(87/179 Pages) STMICROELECTRONICS

87 / 179 page

STM32W108CB, STM32W108HB

General-purpose timers

Doc ID 16252 Rev 2

87/179

The update event can be generated at each counter overflow and at each counter

underflow. Setting the TIM_UG bit in the TIMx_EGR register by software or by using the

slave mode controller also generates an update event. In this case, the both the counter and

the prescalar's counter restart counting from 0.

Software can disable the update event by setting the TIM_UDIS bit in the TIMx_CR1

registers. Then no update event occurs until the TIM_UDIS bit has been written to 0.

However, the counter continues counting up and down, based on the current auto-reload

value.

In addition, if the TIM_URS bit in the TIMx_CR1 register is set, setting the TIM_UG bit

generates an update event, but without setting the INT_TIMUIF flag. Thus no interrupt

request is sent. This avoids generating both update and capture interrupt when clearing the

counter on the capture event.

When an update event occurs, the update flag (the INT_TIMUIF bit in the INT_TIMxFLAG

●

The prescaler shadow register is reloaded with the buffer value (contents of the

TIMx_PSC register).

●

The auto-reload active register is updated with the buffer value (contents of the

TIMx_ARR register). If the update source is a counter overflow, the auto-reload is

updated before the counter is reloaded, so that the next period is the expected one.

The counter is loaded with the new value.

The following figures show some examples of the counter behavior for different clock

frequencies.

Figure 18.

Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6

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