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STM32W108HB bảng dữ liệu(PDF) 113 Page - STMicroelectronics |
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STM32W108HB bảng dữ liệu(HTML) 113 Page - STMicroelectronics |
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113 / 179 page  STM32W108CB, STM32W108HB General-purpose timers Doc ID 16252 Rev 2 113/179 8.3.2 Timer x control register 2 (TIMx_CR2) Address offset: 0xE004 (TIM1) and 0xF004 (TIM2) Reset value: 0x0000 0000 [1] TIM_UDIS: Update Disable 0: An update event is generated as soon as a counter overflow occurs, a software update is generated, or a hardware reset is generated by the slave mode controller. Shadow registers are then loaded with their buffer register values. 1: An update event is not generated and shadow registers keep their value (TIMx_ARR, TIMx_PSC, TIMx_CCRy). The counter and the prescaler are reinitialized if the TIM_UG bit is set or if a hardware reset is received from the slave mode controller. [0] TIM_CEN: Counter Enable 0: Counter disabled. 1: Counter enabled. Note: External clock, gated mode and encoder mode can work only if the TIM_CEN bit has been previously set by software. Trigger mode sets the TIM_CEN bit automatically through hardware. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TIM_TI 1S TIM_MMS rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw [7] TIM_TI1S: TI1 Selection 0: TI1M (input of the digital filter) is connected to TI1 input. 1: TI1M is connected to the TI_HALL inputs (XOR combination). |
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