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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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STM32W108HB bảng dữ liệu(PDF) 112 Page - STMicroelectronics |
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STM32W108HB bảng dữ liệu(HTML) 112 Page - STMicroelectronics |
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112 / 179 page  General-purpose timers STM32W108CB, STM32W108HB 112/179 Doc ID 16252 Rev 2 8.3 General-purpose timer (1 and 2) registers 8.3.1 Timer x control register 1 (TIMx_CR1) Address offset: 0xE000 (TIM1) and 0xF000 (TIM2) Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TIM_A RBE TIM_CMS TIM_D IR TIM_O PM TIM_U RS TIM_U DIS TIM_C EN rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw [7] TIM_ARBE: Auto-Reload Buffer Enable 0: TIMx_ARR register is not buffered. 1: TIMx_ARR register is buffered. [6:5] TIM_CMS: Center-aligned Mode Selection 00: Edge-aligned mode. The counter counts up or down depending on the direction bit (TIM_DIR). 01: Center-aligned mode 1. The counter counts up and down alternatively. Output compare interrupt flags of configured output channels (TIM_CCyS=00 in TIMx_CCMRy register) are set only when the counter is counting down. 10: Center-aligned mode 2. The counter counts up and down alternatively. Output compare interrupt flags of configured output channels (TIM_CCyS=00 in TIMx_CCMRy register) are set only when the counter is counting up. 11: Center-aligned mode 3. The counter counts up and down alternatively. Output compare interrupt flags of configured output channels (TIM_CCyS=00 in TIMx_CCMRy register) are set both when the counter is counting up or down. Note: Software may not switch from edge-aligned mode to center-aligned mode when the counter is enabled (TIM_CEN=1). [4] TIM_DIR: Direction 0: Counter used as up-counter. 1: Counter used as down-counter. [3] TIM_OPM: One Pulse Mode 0: Counter does not stop counting at the next update event. 1: Counter stops counting at the next update event (and clears the bit TIM_CEN). [2] TIM_URS: Update Request Source 0: When enabled, update interrupt requests are sent as soon as registers are updated (counter overflow/underflow, setting the TIM_UG bit, or update generation through the slave mode controller). 1: When enabled, update interrupt requests are sent only when the counter reaches overflow or underflow. |
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