HD64F2149YV datasheet(145/1075 Pages) RENESAS

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Section 5 Interrupt Controller

Rev. 3.00 Jan 18, 2006 page 117 of 1044

REJ09B0280-0300

As interrupt request flags IRQ7F to IRQ0F are set when the setting condition is met, regardless of

the IER setting, only the necessary flags should be referenced.

Interrupts KIN15 to KIN0 and WUE7 to WUE0: Interrupts KIN15 to KIN0 and WUE7 to

WUE0 are requested by input signals at pins

KIN15 to KIN0 and WUE7 to WUE0. When any of

pins

KIN15 to KIN0 or WUE7 to WUE0 are used as key-sense inputs or wakeup events, the

corresponding KMIMR or WUEMR bits should be cleared to 0 to enable those key-sense input

interrupts or wakeup event interrupts. The remaining unused key-sense input KMIMR bits and

WUEMR bits should be set to 1 to disable those interrupts. Interrupts WUE7 to WUE0 and KIN15

to KIN8 correspond to the IRQ7 interrupt, and interrupts KIN7 to KIN0 correspond to the IRQ6

interrupt. Interrupt request generation pin conditions, interrupt request enabling, interrupt control

level setting, and interrupt request status indications, are all in accordance with the IRQ7 and

IRQ6 interrupt settings.

When pins

KIN7 to KIN0, KIN15 to KIN8, or WUE7 to WUE0 are used as key-sense interrupt or

wakeup event interrupt input pins, either low-level sensing or falling-edge sensing must be

designated as the interrupt sense condition for the corresponding interrupt source (IRQ6 or IRQ7).

5.3.2

Internal Interrupts

There are 48 sources for internal interrupts from on-chip supporting modules, plus one software

interrupt source (address break).

• For each on-chip supporting module there are flags that indicate the interrupt request status,

and enable bits that select enabling or disabling of these interrupts. If any one of these is set to

1, an interrupt request is issued to the interrupt controller.

• The interrupt control level can be set by means of ICR.

• The DTC can be activated by an FRT, TMR, SCI, or other interrupt request. When the DTC is

activated by an interrupt, the interrupt control mode and interrupt mask bits have no effect.

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