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HD64F2149YV bảng dữ liệu(PDF) 65 Page - Renesas Technology Corp

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Giải thích chi tiết về linh kiện  Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series
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Section 2 CPU
Rev. 3.00 Jan 18, 2006 page 37 of 1044
REJ09B0280-0300
Exception Vector Table and Memory Indirect Branch Addresses: In normal mode the top area
starting at H'0000 is allocated to the exception vector table. One branch address is stored per 16
bits. The configuration of the exception vector table in normal mode is shown in figure 2.2. For
details of the exception vector table, see section 4, Exception Handling.
H'0000
H'0001
H'0002
H'0003
H'0004
H'0005
H'0006
H'0007
H'0008
H'0009
H'000A
H'000B
Reset exception vector
Exception vector 1
Exception vector 2
Exception
vector table
(Reserved for system use)
Figure 2.2 Exception Vector Table (Normal Mode)
The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses
an 8-bit absolute address included in the instruction code to specify a memory operand that
contains a branch address. In normal mode the operand is a 16-bit word operand, providing a 16-
bit branch address. Branch addresses can be stored in the top area from H'0000 to H'00FF. Note
that this area is also used for the exception vector table.



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