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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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DS72011RB120FPV bảng dữ liệu(PDF) 32 Page - Renesas Technology Corp |
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DS72011RB120FPV bảng dữ liệu(HTML) 32 Page - Renesas Technology Corp |
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32 / 1196 page  Section 1 Overview Rev. 2.00 Sep. 07, 2007 Page 4 of 1164 REJ09B0321-0200 Item Features Bus state controller (BSC) • CSC Seven-channel chip select controller (CSC) External devices with their bus sizes of 32, 16, or 8 bits can be connected Cycle wait function Up to 31 cycles (up to 7 cycles for page access cycle) The following features settable for wait controlling Timings of asserting and negating chip select signals Timings of asserting and negating read/write signals Timings of starting and stopping data output One-write strobe and byte write strobe modes are available as write access modes Page read and page write modes are available as page access modes • SDRAMC Two-channel external SDRAM interfaces Auto refresh using the internal programmable refresh counter or self refresh mode selectable The following features settable Row-column latency, column latency, row-active period, write- recovery period, row precharge period, auto refresh request interval, initial precharge cycle count, and initial auto refresh request interval Random column burst access available (one SDRAM burst length) Initialization sequencer issues precharge and auto refresh commands Bus monitor • Bus monitor function When an illegal address access or a bus timeout is detected, a bus error interrupt is generated. |
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