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DS72011RB120FPV bảng dữ liệu(PDF) 59 Page - Renesas Technology Corp

tên linh kiện DS72011RB120FPV
Giải thích chi tiết về linh kiện  32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
PDF  1196 Pages
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nhà sản xuất  RENESAS [Renesas Technology Corp]
Trang chủ  http://www.renesas.com
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Section 2 CPU
Rev. 2.00 Sep. 07, 2007 Page 31 of 1164
REJ09B0321-0200
Addressing Mode
Instruction Format
Effective Address Calculation
Equation
Register indirect
with displacement
@(disp:4,Rn)
The effective address is the sum of Rn and
a 4-bit displacement (disp). The value of disp is
zero-extended, and remains unchanged for
a byte operation, is doubled for a word
operation, and is quadrupled for a longword
operation.
Rn
Rn + disp
× 1/2/4
+
×
1/2/4
disp
(zero-extended)
Byte:
Rn + disp
Word:
Rn + disp
× 2
Longword:
Rn + disp
× 4
Register indirect
with displacement
@(disp:12,Rn)
The effective address is the sum of Rn and
a 12-bit displacement (disp).
The value of disp is zero-extended.
+
Rn
disp
(zero-extended)
Rn + disp
Byte:
Rn + disp
Word:
Rn + disp
Longword:
Rn + disp
Indexed register
indirect
@(R0,Rn)
The effective address is the sum of Rn and R0.
Rn
R0
Rn + R0
+
Rn + R0
GBR indirect with
displacement
@(disp:8,GBR)
The effective address is the sum of GBR value
and an 8-bit displacement (disp). The value of
disp is zero-extended, and remains unchanged
for a byte operation, is doubled for a word
operation, and is quadrupled for a longword
operation.
GBR
1/2/4
GBR
+ disp
× 1/2/4
+
×
disp
(zero-extended)
Byte:
GBR + disp
Word:
GBR + disp
× 2
Longword: GBR
+ disp
× 4



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