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DS72011RB120FPV bảng dữ liệu(PDF) 54 Page - Renesas Technology Corp

tên linh kiện DS72011RB120FPV
Giải thích chi tiết về linh kiện  32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
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Section 2 CPU
Rev. 2.00 Sep. 07, 2007 Page 26 of 1164
REJ09B0321-0200
2.3
Instruction Features
2.3.1
RISC-Type Instruction Set
Instructions are RISC type. This section details their functions.
(1)
16-Bit Fixed-Length Instructions
Basic instructions have a fixed length of 16 bits, improving program code efficiency.
(2)
32-Bit Fixed-Length Instructions
The SH-2A additionally features 32-bit fixed-length instructions, improving performance and ease
of use.
(3)
One Instruction per State
Each basic instruction can be executed in one cycle using the pipeline system.
(4)
Data Length
Longword is the standard data length for all operations. Memory can be accessed in bytes, words,
or longwords. Byte or word data in memory is sign-extended and handled as longword data.
Immediate data is sign-extended for arithmetic operations or zero-extended for logic operations. It
is also handled as longword data.
Table 2.2
Sign Extension of Word Data
SH-2A CPU
Description
Example of Other CPU
MOV.W
@(disp,PC),R1
ADD
R1,R0
.........
.DATA.W
H'1234
Data is sign-extended to 32
bits, and R1 becomes
H'00001234. It is next
operated upon by an ADD
instruction.
ADD.W
#H'1234,R0
Note:
@(disp, PC) accesses the immediate data.



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