DS72011RB120FPV datasheet(25/1196 Pages) RENESAS

25 / 1196 page

Rev. 2.00 Sep. 07, 2007 Page xxv of xxviii

22.2.2 Port B Data Registers H and L (PBDRH and PBDRL) ........................................ 908

22.2.3 Port B Port Registers H and L (PBPRH and PBPRL)........................................... 910

22.3

Port C ................................................................................................................................. 911

22.3.1 Register Configuration.......................................................................................... 911

22.3.2 Port C Data Registers H and L (PCDRH and PCDRL) ........................................ 912

22.3.3 Port C Port Registers H and L (PCPRH and PCPRL)........................................... 913

22.4

Port D................................................................................................................................. 914

22.4.1 Register Configuration.......................................................................................... 914

22.4.2 Port D Data Register (PDDR)............................................................................... 915

22.4.3 Port D Port Registers H and L (PDPRH and PDPRL) .......................................... 916

22.5

Port E ................................................................................................................................. 917

22.5.1 Register Configuration.......................................................................................... 917

22.5.2 Port E Port Register (PEPR) ................................................................................. 917

22.6

Port F ................................................................................................................................. 918

22.6.1 Register Configuration.......................................................................................... 918

22.6.2 Port F Data Register (PFDR) ................................................................................ 919

22.6.3 Port F Port Register (PFPR).................................................................................. 920

Section 23 Pin Function Controller (PFC).........................................................921

23.1

Register Descriptions ......................................................................................................... 929

23.1.1 Port A I/O Registers H and L (PAIORH and PAIORL) ....................................... 931

23.1.2 Port A Control Registers 1 to 8 (PACR1 to PACR8) ........................................... 932

23.1.3 Port B I/O Registers H and L (PBIORH and PBIORL) ........................................ 942

23.1.4 Port B Control Registers 1 to 8 (PBCR1 to PBCR8) ............................................ 943

23.1.5 Port C I/O Registers H and L (PCIORH and PCIORL) ........................................ 956

23.1.6 Port C Control Registers 1 to 7 (PCCR1 to PCCR7) ............................................ 957

23.1.7 Port D I/O Register (PDIOR)................................................................................ 967

23.1.8 Port D Control Registers 1 to 5 (PDCR1 to PDCR5) ........................................... 968

23.1.9 Port E Control Registers 1 and 2 (PECR1 and PECR2) ....................................... 975

23.1.10 Port F I/O Register (PFIOR) ................................................................................. 978

23.1.11 Port F Control Registers 1 and 2 (PFCR1 and PFCR2) ........................................ 979

23.2

Usage Note......................................................................................................................... 982

Section 24 On-Chip RAM .................................................................................983

24.1

Features.............................................................................................................................. 983

24.2

Usage Notes ....................................................................................................................... 984

24.2.1 Page Conflict ........................................................................................................ 984

24.2.2 RAME and RAMWE Bits .................................................................................... 984

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