DS72011RB120FPV datasheet(14/1196 Pages) RENESAS

14 / 1196 page

Rev. 2.00 Sep. 07, 2007 Page xiv of xxviii

9.4.4

CSn Mode Register (CSMODn) (n = 0 to 6) ........................................................ 214

9.4.5

CSn Wait Control Register 1 (CS1WCNTn) (n = 0 to 6) ..................................... 217

9.4.6

CSn Wait Control Register 2 (CS2WCNTn) (n = 0 to 6) ..................................... 219

9.4.7

SDRAM Refresh Control Register 0 (SDRFCNT0) ............................................. 222

9.4.8

SDRAM Refresh Control Register 1 (SDRFCNT1) ............................................. 223

9.4.9

SDRAM Initialization Register 0 (SDIR0)........................................................... 225

9.4.10 SDRAM Initialization Register 1 (SDIR1)........................................................... 227

9.4.11 SDRAM Power-Down Control Register (SDPWDCNT) ..................................... 228

9.4.12 SDRAM Deep-Power-Down Control Register (SDDPWDCNT) ........................ 229

9.4.13 SDRAMm Address Register (SDmADR) (m = 0, 1)............................................ 230

9.4.14 SDRAMm Timing Register (SDmTR) (m = 0, 1) ................................................ 231

9.4.15 SDRAMm Mode Register (SDmMOD) (m = 0, 1)............................................... 233

9.4.16 SDRAM Status Register (SDSTR) ....................................................................... 234

9.4.17 SDRAM Clock Stop Control Signal Setting Register (SDCKSCNT) .................. 236

9.4.18 AC Characteristics Switching Register (ACSWR) ............................................... 237

9.5

Operation ........................................................................................................................... 238

9.5.1

CSC Interface........................................................................................................ 238

9.5.2

SDRAM Interface ................................................................................................. 248

9.6

Usage Note......................................................................................................................... 285

9.6.1

Note on Power-on Reset Exception Handling and

Deep Standby Mode Cancellation ........................................................................ 285

9.6.2

Write Buffer.......................................................................................................... 285

9.6.3

Note on Transition to Software Standby Mode or Deep Standby Mode............... 285

Section 10 Bus Monitor..................................................................................... 287

10.1

Register Descriptions ......................................................................................................... 287

10.1.1 Bus Monitor Enable Register (SYCBEEN) .......................................................... 288

10.1.2 Bus Monitor Status Register 1 (SYCBESTS1)..................................................... 289

10.1.3 Bus Monitor Status Register 2 (SYCBESTS2)..................................................... 291

10.1.4 Bus Error Control Register (SYCBESW)............................................................. 294

10.2

Bus Monitor Function ........................................................................................................ 295

10.2.1 Operation when a Bus Error is Detected............................................................... 295

10.2.2 Illegal Address Access Detection Function .......................................................... 296

10.2.3 Bus Timeout Detection Function .......................................................................... 298

10.2.4 Combinations of Masters and Bus Errors ............................................................. 299

10.3

Usage Note......................................................................................................................... 300

10.3.1 Operation when the CPU is Not Notified of a Bus Error...................................... 300

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