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DS72011RB120FPV bảng dữ liệu(PDF) 135 Page - Renesas Technology Corp |
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DS72011RB120FPV bảng dữ liệu(HTML) 135 Page - Renesas Technology Corp |
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135 / 1196 page ![]() Section 5 Exception Handling Rev. 2.00 Sep. 07, 2007 Page 107 of 1164 REJ09B0321-0200 5.7 Exceptions Triggered by Instructions 5.7.1 Types of Exceptions Triggered by Instructions Exception handling can be triggered by trap instructions, general illegal instructions, slot illegal instructions, and integer division exceptions, as shown in table 5.10. Table 5.10 Types of Exceptions Triggered by Instructions Type Source Instruction Comment Trap instruction TRAPA Slot illegal instructions Undefined code placed immediately after a delayed branch instruction (delay slot), instructions that rewrite the PC, 32-bit instructions, RESBANK instruction, DIVS instruction, and DIVU instruction Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF, BRAF Instructions that rewrite the PC: JMP, JSR, BRA, BSR, RTS, RTE, BT, BF, TRAPA, BF/S, BT/S, BSRF, BRAF, JSR/N, RTV/N 32-bit instructions: BAND.B, BANDNOT.B, BCLR.B, BLD.B, BLDNOT.B, BOR.B, BORNOT.B, BSET.B, BST.B, BXOR.B, MOV.B@disp12, MOV.W@disp12, MOV.L@disp12, MOVI20, MOVI20S, MOVU.B, MOVU.W. General illegal instructions Undefined code anywhere besides in a delay slot Division by zero DIVU, DIVS Integer division exceptions Negative maximum value ÷ (−1) DIVS Floating-point operation instruction Instructions that cause disabled operation exception defined by IEEE754 standard or division exception by zero. Instructions that could cause overflow, underflow, or imprecise exception. FADD, FSUB, FMUL, FDIV, FMAC, FCMP/EQ, FCMP/GT, FLOAT, FTRC, FCNVDS, FCNVSD, FSQRT |
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