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DS72011RB120FPV bảng dữ liệu(PDF) 129 Page - Renesas Technology Corp

tên linh kiện DS72011RB120FPV
Giải thích chi tiết về linh kiện  32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
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nhà sản xuất  RENESAS [Renesas Technology Corp]
Trang chủ  http://www.renesas.com
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DS72011RB120FPV bảng dữ liệu(HTML) 129 Page - Renesas Technology Corp

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Section 5 Exception Handling
Rev. 2.00 Sep. 07, 2007 Page 101 of 1164
REJ09B0321-0200
5.3
Address Errors
5.3.1
Address Error Sources
Address errors occur when instructions are fetched or data read or written, as shown in table 5.7.
Table 5.7
Bus Cycles and Address Errors
Bus Cycle
Type
Bus
Master
Bus Cycle Description
Address Errors
Instruction fetched from even address
None (normal)
Instruction fetched from odd address
Address error occurs
Instruction fetched from area other than
H'F0000000 to H'F5FFFFFFF in cache
address array space*
1
None (normal)
Instruction
fetch
CPU
Instruction fetched from H'F0000000 to
H'F5FFFFFFF in cache address array
space*
1
Address error occurs
Word data accessed from even address
None (normal)
Word data accessed from odd address
Address error occurs
Longword data accessed from a
longword boundary
None (normal)
Longword data accessed from other than
a long-word boundary
Address error occurs
Byte or word data accessed in on-chip
peripheral module space*
2
None (normal)
Longword data accessed in 16-bit on-
chip peripheral module space*
2
None (normal)
Data
read/write
CPU
Longword data accessed in 8-bit on-chip
peripheral module space*
2
None (normal)
Notes: 1. For details on cache address array space, see section 8, Cache.
2. For details on peripheral module space, see section 9, Bus State Controller (BSC).



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