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DS72011RB120FPV bảng dữ liệu(PDF) 111 Page - Renesas Technology Corp

tên linh kiện DS72011RB120FPV
Giải thích chi tiết về linh kiện  32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
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Section 4 Clock Pulse Generator (CPG)
Rev. 2.00 Sep. 07, 2007 Page 83 of 1164
REJ09B0321-0200
4.4
Register Descriptions
The clock pulse generator has the following registers.
Table 4.4
Register Configuration
Register Name
Abbreviation R/W
Initial Value Address
Access Size
Frequency control register
FRQCR
R/W
H'1003
H'FFFE0010 16
CKIO control register
CKIOCR
R/W
H'10/H'00
H'FFFE3894 8, 16, 32
4.4.1
Frequency Control Register (FRQCR)
FRQCR is a 16-bit readable/writable register used to specify whether a clock is output from the
CKIO pin in software standby mode, the frequency multiplication ratio of PLL circuit 1, and the
frequency division ratio of the internal clock and peripheral clock (P
φ). Only word access can be
used on FRQCR.
FRQCR is initialized to H'1003 only by a power-on reset or in deep standby mode. FRQCR retains
its previous value by a manual reset or in software standby mode. The previous value is also
retained when an internal reset is triggered by an overflow of the WDT.
15
14
13
12
11
10
987654321
0
0001000000000011
R
R
R
R/W
R
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
Initial value:
R/W:
———
CKOEN
—
STC[2:0]
—
IFC[2:0]
RNGS
PFC[2:0]
Bit
Bit Name
Initial
Value
R/W
Description
15 to 13
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.



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