DS72011RB120FPV datasheet(101/1196 Pages) RENESAS

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Section 4 Clock Pulse Generator (CPG)

Rev. 2.00 Sep. 07, 2007 Page 73 of 1164

REJ09B0321-0200

Section 4 Clock Pulse Generator (CPG)

This LSI has a clock pulse generator (CPG) that generates an internal clock (I

φ), a peripheral clock

φ), and a bus clock (Bφ). The CPG consists of a crystal oscillator, PLL circuits, and divider

circuits.

4.1

Features

• Three clock operating modes

The mode is selected from among the three clock operating modes by the selection of the

following three conditions: the frequency-divisor in use, whether the PLLs are on or off, and

whether the internal crystal resonator or the input on the external clock-signal line is used.

• Three clocks generated independently

An internal clock (I

φ) for the CPU and cache; a peripheral clock (Pφ) for the on-chip

peripheral modules; a bus clock (B

φ = CKIO) for the external bus interface.

• Frequency change function

Internal and peripheral clock frequencies can be changed independently using the PLL (phase

locked loop) circuits and divider circuits within the CPG. Frequencies are changed by software

using frequency control register (FRQCR) settings.

• Power-down mode control

The clock can be stopped by sleep mode, software standby mode, and deep standby mode.

Specific modules can also be stopped using the module standby function. For details on clock

control in the power-down modes, see section 25, Power-Down Modes.

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