HD4046212RFS datasheet(15/157 Pages) RENESAS

15 / 157 page

HD404629R Series

Bit 3

Bit 2

Bit 1

Bit 0

IMTA

(IM of timer A)

IFTA

(IF of timer A)

IM1

(IM of

INT1)

IF1

(IF of

INT1)

IMTC

(IM of timer C)

IFTC

(IF of timer C)

IMTB

(IM of timer B)

IFTB

(IF of timer B)

IMAD

(IM of A/D)

IFAD

(IF of A/D)

IMTD

(IM of timer D)

IFTD

(IF of timer D)

$000

$001

$002

$003

Interrupt control bits area

IM0

(IM of

INT0)

IF0

(IF of

INT0)

RSP

(Reset SP bit)

(Interrupt

enable flag)

ICSF

(Input capture

status flag)

IM3

(IM of INT3)

IF3

(IF of INT3)

IM2

(IM of INT2)

IF2

(IF of INT2)

IMS

(IM of serial

interface)

IFS

(IF of serial

interface)

IM4

(IM of INT4)

IF4

(IF of INT4)

$020

$021

$022

$023

DTON

(Direct transfer

on flag)

ADSF

(A/D start flag)

WDON

(Watchdog

on flag)

LSON

(Low speed

on flag)

ICEF

(Input capture

error flag)

RAME

(RAM enable

flag)

Not used

IF:

IM:

IE:

SP:

Interrupt request flag

Interrupt mask

Interrupt enable flag

Stack pointer

Bit 3

Bit 2

Bit 1

Bit 0

Figure 3 Configuration of Interrupt Control Bits and Register Flag Areas

LSON

ICSF

ICEF

RAME

RSP

WDON

ADSF

Not used

DTON

SEM/SEMD

REM/REMD

TM/TMD

Allowed

Not executed

Allowed

Not executed

Allowed

Inhibited

Allowed

Not executed

Inhibited

Allowed

Inhibited

Allowed

Not executed in active mode

Allowed

Used in subactive mode

Not executed

Inhibited

Note: WDON is reset by MCU reset or by

STOPC enable for stop mode cancellation.

The REM or REMD instuction must not be executed for ADSF during A/D conversion.

DTON is always reset in active mode.

If the TM or TMD instruction is executed for the inhibited bits or non-existing bits,

the value in ST becomes invalid.

Figure 4 Usage Limitations of RAM Bit Manipulation Instructions

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