TAS2781RYYR datasheet(76/90 Pages) TI2

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12 Layout

12.1 Layout Guidelines

All supply rails should be bypassed by low-ESR ceramic capacitors as shown and described in Section 9.2.

To create a low impedance connection to PGND, DGND and GND and minimize the ground noise, ground

planes with multiple conductive epoxy filled vias should be used in layout.

Specific layout design recommendations should be followed for this device:

• Use wide traces for signals that carry high current: PVDDH, PVDDL, PGND, DGND, GND and the speaker

OUTP, OUTN.

• PGND pin should be directly connected and shorted to the ground plane.

• DGND pin should be directly connected to the ground plane.

• Connect VSNSP and VSNSN as close as possible to the speaker.

• VSNSP and VSNSN should be connected between the EMI ferrite filter and the speaker if EMI ferrites are

used at the outputs.

• VSNSP and VSNSN routing should be separated and shielded from switching signals (interface signals,

speaker outputs, bootstrap pins).

• Place bootstrap capacitors as close as possible to the BST pins.

• Place decoupling capacitors of PVDDH and PVDDL as close as possible to the pins (see Section 12.2).

12.2 Layout Example

Figure 12-1 below describes the placement of critical components as assigned in Figure 9-1.

Figure 12-1. Component Placement

An example of layout design is presented in the next two images.

TAS2781

SLOSE86B – JULY 2022 – REVISED JULY 2023

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TAS2781RYYR bảng dữ liệu(PDF) 76 Page - Texas Instruments