TAS2781RYYR datasheet(26/90 Pages) TI2

26 / 90 page

The bits from register in enable the ICC feature and set the device pairing and gain transmiting slots.

The sampling rates of 16 kHz and 24 kHz (and 44.1 kHz equivalent) are not supported in this mode of operation.

8.4.2.12 Class-D Settings

8.4.2.12.1 Output Slew Rate Control

The output slew rate can be programmed using bits EDGE_CTRL[1:0] from register in .

By default, if PVDDH supply is below 20 V the output slew rate will be at a fast rate, dependant on supply and

load. If PVDDH goes above 20 V the slew rate will be automatically change to a slower rate.

Optionally, to improve EMI performance, user can set the slew rate to a slower rate for the entire range of

PVDDH supply by setting the bits EDGE_CTRL[1:0] to 2'b11.

8.4.2.12.2 Synchronization

The TAS2781 Class-D amplifier supports spread spectrum PWM modulation, which can be enabled by setting

the AMP_SS register bit high. This can help reduce EMI in the system.

By default the Class-D amplifier switching frequency is based on the device trimmed internal oscillator. To

synchronize switching to the audio sample rate, set the CLASSD_SYNC register bit high. When the Class-D is

synchronized to the audio sample rate, the RAMP_RATE register bit must be set depending on the audio sample

rate of either 44.1 kHz or 48 kHz (default) based frequency.

8.4.3 SAR ADC

A SAR ADC monitors PVDDH voltage, PVDDL voltage and die temperature. The results of these conversions

are available via register readback (PVDDH_CNV[11:0], PVDDL_CNV[11:0] and TMP_CNV[7:0] register bits).

PVDDH and PVDDL voltage conversions are also used by the limiter and brown out prevention blocks.

By default, PVDDL conversion is enabled along with PVDDH and temperature in both cases, when BOP source

is PVDDL (BOP_SRC = 0) or BOP source is PVDDH (BOP_SRC = 1).

The ADC runs at a fixed 192 kHz sample rate with a conversion time of 5.2 µs.

Temperature is sampled once every 18th SAR conversions. Sampling rate for temperature is approximative 10K

samples/sec.

PVDDH and PVDDL voltages and the die temperature can be estimated by user using equations from registers

in , and .

The register bits content should always be read from MSB to LSB.

The voltage and temperature readings of SAR ADC are also available to the host through the SDOUT pin. Use

bits of register from to enable this feature and configure the slots.

8.4.4 Current and Voltage (IV) Sense

The TAS2781 provides speaker voltage and current sense measurements for real time monitoring of

loudspeaker behavior. The VSNSP and VSNSN pins should be connected after any ferrite bead filter (or directly

to the OUTP and OUTN connections if no EMI filter is used). The V-Sense connections eliminate voltage

drop error due to packaging, PCB interconnect or ferrite bead filter resistance. It should be noted that any

interconnect resistance after the VSNS terminals will not be corrected for, so it is advised to connect the sense

connections as close to the load as possible.

The voltage and current sense internal ADCs have a DC blocking filter. This filter cut-off frequency can be

adjusted, or the filter can be bypassed using the HPF_FREQ_REC[2:0] register bits.

I-Sense and V-Sense blocks can be powered up by setting the ISNS_PD and VSNS_PD register bits to low.

8.4.5 Post Filter Feed-Back (PFFB)

The device supports post-filter feedback by closing the amplifier feedback loop after the external filter. The

feedback is applied using the VSNSN and VSNSP terminals of the device. This feature can be disabled using

TAS2781

SLOSE86B – JULY 2022 – REVISED JULY 2023

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