TAS2781RYYR datasheet(53/90 Pages) TI2

53 / 90 page

8.9.58 Page = 0x00 Address = 0x67 [Reset = 00h]

Bit

Field

Type

Reset

Description

7-2

Reserved

00h

Reserved

1-0

IDCH_HYST[1:0]

Idle channel hysterisis timer

0h = 50 ms (default)

1h = 100 ms

2h = 200 ms

3h = 1000 ms

*For sampling rates fs < 48 ksps multiply the values by 48/fs

8.9.59 Page = 0x00 Address = 0x68 [Reset = 30h]

Bit

Field

Type

Reset

Description

7-6

Reserved

5-0

FS_RATIO[5:0]

30h

Detected SBCLK to FSYNK ratio. See Table 8-10.

Table 8-10. Detected SBCLK to FSYNC Ratio

00h = 16

01h = 24

02h = 32

03h = 48

04h = 64

05h = 96

06h = 128

07h = 192

08h = 256

09h = 384

0Ah = 512

0Bh = 125

0Ch = 250

0Dh = 500

0Eh - 3Fh = Reserved

8.9.60 Page = 0x00 Address = 0x6A [Reset = 12h]

Bit

Field

Type

Reset

Description

7-6

CDS_DLY[1:0]

Delay (1/fs) of the Y-bridge switching with respect to the input

signal. See Table 8-11.

5-4

LVS_DLY[1:0]

Delay (1/fs) of the PWM_CTRL pin signaling with respect to the

input signal, when Class H is disabled. See Table 8-12.

3-0

LVS_RTH[3:0]

Relative threshold for Low Voltage Signaling (headroom from

PVDDL voltage).

0h = 0.5 V

1h = 0.6 V

2h = 0.7 V

...

Eh = 1.9 V

Fh = 2 V

Table 8-11. CDS Delay (1/fs)

48 ksps

96 ksps

NG Enabled

NG Disabled

NG Enabled

NG Disabled

0h (default)

8.1

6.1

12.6

9.6

7.1

5.1

10.6

7.6

6.1

4.1

8.5

5.6

3.6

7.6

4.6

Table 8-12. LVS_Delay (1/fs)

48 ksps

96 ksps

NG Enabled

NG Disabled

NG Enabled

NG Disabled

7.8

5.8

12.1

9.1

1h (default)

6.8

4.8

10.1

7.1

5.8

3.8

8.1

5.1

3.1

6.6

3.6

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TAS2781

SLOSE86B – JULY 2022 – REVISED JULY 2023

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