TAS2781RYYR datasheet(25/90 Pages) TI2

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voltage will be dynamically set 10% below the current PVDDH. In this use case the limiting will begin at signal

levels lower than the supply voltage and prevent clipping from occurring.

To achieve a limiter that tracks PVDDH only up to a minimum threshold, configure the limiter LIM_MAX_TH[31:0]

and LIM_SLP[31:0] register bits as in the previous examples. Then additionally set the LIM_MIN_TH[31:0]

decrease the signal output voltage. This is shown in .

By setting register bit LIM_DYHDR to low the limiter mechanism depends on settings for maximum and minimum

thresholds, inflection point and slope. By default this bit is high and the limiter dynamic headroom is enabled.

8.4.2.10 Brownout Prevention

Brownout Prevention (BOP) feature provides a priority input to the limiter to generate a fast response to transient

dips in supply voltage at end of charge conditions that can cause system level brownout. When supply voltage

dips below the BOP threshold, the limiter begins reducing gain at a configurable attack rate. When supply

voltage rises above the BOP threshold, the limiter will begin to release after the programmed hold time. The

BOP feature can be enabled by setting the BOP_EN[0] register bit high. The brownout supply source can be set

using BOP_SRC register bit to either PVDDH or PVDDL depending on application.

By default BOP supply source is set to PVDDL input and the SAR converter will digitize the PVDDH and PVDDL

voltages and temperature. The PVDDH undervoltage detection will be disabled.

When BOP supply source is set to PVDDH input the SAR ADC converter willl digitize the PVDDH and PVDDL

voltages and temperature. The PVDDH undervoltage detection will be enabled in this case.To reduce latency in

the first attack of the BOP engine, PVDDL conversion can be bypassed by setting the register bit CNV_PVDDLto

low.

When BOP supply source is set to PVDDL input the SAR converter willl digitize the PVDDH and PVDDL

voltages and temperature. The PVDDH undervoltage detection will be disabled.

When the BOP is engaging the Supply Tracking Limiter is paused.

The BOP threshold is set by the BOP_TH[31:0] bits from registers in . The setting of BOP_MUTE bit determines

if once the supply goes below the threshold the device mutes audio and shuts down or just attenuates the audio

signal whit no muting.

The TAS2781 can also immediately mute and then shutdown the device when a BOP event occurs by reaching

the threshold set by the BOPSD_TH[31:0] bits from registers in if the BOPSD_EN register bit is set high. This

shutdown feature is auto disabled internally when BOP_MUTE is set high.

The BOP has programmable attack rate register bits BOP_ATK[2:0], attack step size register bits

BOP_ATK_ST[1:0] and hold time register bits BOP_HLD[2:0]).

When the system comes out of BOP the supply tracking limiter release will be engaged. If the limiter is disabled

the gain will be released as per limiter release settings.

The hold time can be set to Infinite by programming the BOP_INF_HLD register bit to high. The device will need

to transition through a mute or SW/HW shutdown state or the register bit BOP_HLD_CLR can be set to high

(which will cause the device to exit the hold state and begin releasing).

When BOP_INF_HLD bit is set low the device will hold based on programming of BOP_HLD[2:0] bits.

8.4.2.11 ICC Pin and Inter-Chip Communication

The TAS2781 supports dual gain balancing in stereo applications. One device can be paired with only one other

device in the system.

The ICC pin will be connected to an ICC bus with bus keeper. Pin 17 (NC_V1P8V) supplying ICC buffer needs to

be connected to an 1.8 V supply.

The SDOUT pin cannot be used for gain alignment.

The ICC_CFG[2:0] bits of register from configure the functionality of the ICC pin.

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TAS2781

SLOSE86B – JULY 2022 – REVISED JULY 2023

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