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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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TAS2781RYYR bảng dữ liệu(PDF) 37 Page - Texas Instruments |
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TAS2781RYYR bảng dữ liệu(HTML) 37 Page - Texas Instruments |
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37 / 90 page  Bit Field Type Reset Description 5-4 SDZ_TMOUT[1:0] RW 2h Shutdown timeout 0h = 2 ms 1h = 4 ms 2h = 6 ms (default) 3h = 23.8 ms 3-2 DVC_RMP_RT[1:0] RW 0h Digital volume control ramp rate 0h = Volume ramp enabled (default) 1h - 2h = Reserved 3h = Volume ramp disabled 1 I2C_GBL_EN RW 0h I2C global address 0h = Disabled 1h = Enabled 0 I2C_AD_DET RW 0h Re-detect I2C peripheral address (self clearing bit) 0h = Normal detection 1h = Re-detect address after power up 8.9.9 Page = 0x00 Address = 0x08 [Reset = 09h] Bit Field Type Reset Description 7 AMP_INV RW 0h Invert audio amplifier ouput 0h = Normal 1h = Inverted 6 CLASSD_SYNC RW 0h Class-D synchronization mode 0h = Not synchronized to audio clocks 1h = Synchronized to audio clocks *When Spread Spectrum and Sync Mode are both enabled, Sync Mode takes priority 5 RAMP_RATE RW 0h When CLASSD_SYNC = 1 sample rate is based 0h = 48 kHz 1bh = 44.1 kHz 4 AUTO_RATE RW 0h Auto-detection of TDM sample rate 0h = Enabled 1h = Disabled 3-1 SAMP_RATE[2:0] RW 4h Sample rate of the TDM bus 0h = Reserved 1h = 14.7/16 kHz 2h = 22.05/24 kHz 3h = 29.4/32 kHz 4h = 44.1/48 kHz 5h = 88.2/96 kHz 6h = 176.4/192 kHz 7h = Reserved 0 FRAME_START RW 1h TDM frame start polarity 0h = Low to High on FSYNC 1h = High to Low on FSYNC 8.9.10 Page = 0x00 Address = 0x09 [Reset = 02h] Bit Field Type Reset Description 7 RMP_FREQ_INCR RW 0h When CLASSD_SYNC = 1, ramp rate is 0h = 352 kHz 1h = 376 kHz 6 RX_JSTF RW 0h TDM RX sample justification within the time slot 0h = Left 1h = Right 5-1 RX_OFF[4:0] RW 1h TDM RX start of frame to time slot 0 offset (number of SBCLK cycles) www.ti.com TAS2781 SLOSE86B – JULY 2022 – REVISED JULY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 37 Product Folder Links: TAS2781 |
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