TAS2781RYYR datasheet(22/90 Pages) TI2

22 / 90 page

8.4.2.3 Amplifier Inversion

The TAS2781 will output a non-inverted signal to the OUT_P and OUT_N pins. The output can be inverted with

respect to the digital input value by setting the AMP_INV register bit to high.

8.4.2.4 Digital Volume Control and Amplifier Output Level

The gain from audio input to speaker terminals is controlled by setting the amplifier output level and the digital

volume control (DVC).

Amplifier output level settings are programmed using the AMP_LVL[4:0] register bits. The amplifier levels are

presented in the register from . The Digital Volume Control (DVC) is set by default to 0 dB. It should be noted

that these levels may not be achievable because of analog clipping in the amplifier, so they should be used only

to convey gain.

Equation (1) calculates amplifier output voltage:

VAMP= INPUT+ADVC+AAMP

(1)

where

• VAMP is the amplifier output voltage in dBV

• INPUT is the digital input amplitude as a number of dB with respect to 0 dBFS

• ADVC is the digital volume control setting as a number of dB

• AAMP is the amplifier output level setting as a number of dBV

The DVC is configurable from 0 dB to -100 dB in 0.5 dB steps by setting the DVC_LVL[7:0] register bits. Settings

greater than C8h are interpreted as mute. When a change in digital volume control occurs, the device ramps the

volume to the new setting based on the DVC_SLEW[31:0] register bits status from . The bits DVC_RMP_RT[1:0]

of register in enable or disable the volume ramp control

The Class-D amplifier uses a closed-loop architecture. The approximate threshold for output signal clipping is

given by equation (2).

(2)

where:

• VPK is the maximum peak un-clipped output voltage in V

• VSUP is the power supply of Class-D output stage

• RL is the speaker load in Ω

• RP is the parasitic resistance on PCB (routing, filters) in Ω

• RFET is the power stage total resistance (HS FET, LS FET, Sense Resistor, bonding, packaging) in Ω

When PVDDL supplies Class-D output stage typical RFET value is 0.5 Ω. For PVDDH supply RFET typical value

is 0.25 Ω.

8.4.2.5 PVDDL Supply

The TAS2781 can operate with or without a PVDDL supply. When configured without a PVDDL supply, the

PVDDH voltage will be used with an internal LDO to generate this supply voltage. A decoupling capacitor should

still be populated as recommended in Table 9-1. In this case, PVDDL_MODE bit should be set to high before

transitioning from Software Shutdown mode. More details about PVDDL supply modes of operation can be found

in Section 11.1.

8.4.2.6 Y - Bridge

The TAS2781 Class-D output uses a Y-Bridge configuration to improve efficiency during playback. The LVS

() is internally used to select between the PVDDH and PVDDL supplies. This feature is enabled by setting

CDS_MODE[1:0] bits to 2'b00 when both PVDDH and PVDDL are supplied to the device. If not configured to

TAS2781

SLOSE86B – JULY 2022 – REVISED JULY 2023

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