TAS2781RYYR datasheet(20/90 Pages) TI2

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ADDR pin when SDZ pin is released. Additionally, the address may be re-detected by setting I2C_AD_DET

8.3.3 SPI Interface

TAS2781 features an 1.8 V SPI interface when pin 26 (MODE) is connected to GND through a 470 Ω resistor.

Pin 17 (NC_V1P8) of the device needs to be tied to an 1.8 V supply.

The host controller should use the mode with CPHA = 1 and CPOL = 0. The TAS2781 SPI logic block is

sampling SPI input data on falling edge of SPI clock and transmiting SPI output data on rising edge of SPI clock.

8.3.4 Register Organization

Device configuration and coefficients are stored using a page and book scheme. Each page contains 128 bytes

and each book contains 256 pages. All device configuration registers are stored in book 0 which is the default

setting at power up and after a software reset. The book and page can be set by the BOOK[7:0] bits of register

from and PAGE[7:0] bits of register from .

Note

Programming register bits from book 0x00, pages 0x04, 0x05, 0x06, 0x08 and 0x0A needs to be

done in groups of four registers (32 bit format), each byte corresponding to an 8 bit register and with

less significant byte corresponding to the highest register address. For instance , when programming

the limiter maximum threshold in registers from , the MSBs will be in register 0x10 and the LSBs in

8.4 Device Functional Modes

8.4.1 TDM Serial Audio Port

The TAS2781 provides a flexible TDM serial audio port. The port can be configured to support a variety of

formats including stereo I2S, Left Justified and TDM. Mono audio playback is available via the SDIN pin. The

SDOUT pin is used to transmit sample streams including PVDDL voltage, PVDDH voltage, die temperature,

status, audio for echo cancelation.

By default, the TAS2781 will automatically detect the PCM playback sample rate (AUTO_RATE= 0). This can be

disabled and manually configured by setting the AUTO_RATE bit of register in to high.

The TDM serial audio port valid SBCLK to FSYNC ratios are presented in register in . The device will

automatically detect the number of time slots and it does not need to be programmed.

The SAMP_RATE[2:0] and SBLK_FS_RATIO[5:0] register bits are used to configure the PCM audio sample rate

when AUTO_RATE register bit is high (auto detection of TDM sample rate is disabled). The TAS2781 employs

a robust clock fault detection engine that will automatically volume ramp down the playback path if FSYNC does

not match the configured sample rate (if AUTO_RATE = 1) or the ratio of SBCLK to FSYNC is not supported

(minimizing any audible artifacts). Once the clocks are detected to be valid in both frequency and ratio, the

device will automatically volume ramp the playback path back to the configured volume and resume playback.

When using the auto rate detection the sampling rate and SBCLK to FSYNC ratio detected on the TDM bus is

reported back on the read-only bits FS_RATIO[5:0] and FS_RATE[2:0] of registers in ] and in .

A frame begins with the transition of FSYNC from either high to low or low to high (set by the FRAME_START

RX_EDGE register bit). The RX_OFF[4:0] register bits define the number of SBCLK cycles from the transition of

FSYNC until the beginning of time slot 0. This is typically set to a value of 0 for Left Justified format and 1 for an

I2S format.

The RX_SLEN[1:0] register bits set the length of the RX time slot to 16, 24 or 32 (default) bits. The length of

the audio sample word within the time slot is configured by the RX_WLEN[1:0] register bits. The RX port will

left justify the audio sample within the time slot by default, but this can be changed to right justification via the

RX_JSTF register bit. The TAS2781 supports mono and stereo down mix playback ([L+R]/2). By default the

device will playback mono from the time slot equal to the I2C base address offset (set by the ADDR pin) for

TAS2781

SLOSE86B – JULY 2022 – REVISED JULY 2023

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