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MPL460AT-I/4LB bảng dữ liệu(PDF) 7 Page - Microchip Technology |
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MPL460AT-I/4LB bảng dữ liệu(HTML) 7 Page - Microchip Technology |
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7 / 48 page ![]() PL460 Signal Description Data Sheet © 2020-2023 Microchip Technology Inc. and its subsidiaries DS60001666D - 7 3. Signal Description Table 3-1. Signal Description List Signal Name Function Type Active Level Voltage Reference Comments Power Supplies VDDIO 3.3V Digital supply Power — — 3.0V to 3.6V (Note 1) VDDIN 3.3V Voltage input for core voltage regulator Power — — 3.0V to 3.6V (Note 1) VDDIN_AN 3.3V Analog supply (ADC + PGA) Power — — 3.0V to 3.6V (Note 2) VDDCORE 1.25V Voltage Regulator Output with internal connection to Core power supply Power — — 1.25V (Note 3) VDDPLL 1.25V PLL power supply input. Must be connected to VDDCORE through a LP filter Power — — 1.25V (Note 4) VREGP PLC Driver voltage regulator output for external decoupling capacitor Power — — (Note 5) VREGN PLC Driver voltage regulator output for external decoupling capacitor Power — — (Note 6) PVDDAMP Power supply of PLC driver amplifier and regulators Power — — 8V to 16V (Note 7, 8) VDDAMP 3.3V Digital and analog power supply of PLC driver Power — — 3.0 to 3.6V (Note 9) GND Digital ground Power — — (Note 10) AGND Analog ground Power — — (Note 10) PGND Power ground of PLC driver Power — — (Note 10) GNDAMP Analog ground of PLC driver Power — — (Note 10) Clocks, Oscillators and PLLs XIN Crystal Oscillator Input Input — VDDIO — XOUT Crystal Oscillator Output Output — VDDIO — Reset/Enable NRST System Reset Input Low VDDIO (Note 11) ENABLE Enable Internal core voltage regulator Input High VDDIO — Power Line Communications OUT Switching amplifier output Output — PVDDAMP — ASO[0:1] Analog Switch Outputs to disable the bandpass filtering when there is no PLC transmission activity Output — PVDDAMP High-voltage, high-current, and low resistance analog switches. ASI[0:1] Analog Switch status Output — VDDIO — VIN PLC signal reception input Input — VDDIN_AN — AGC Automatic Gain Control. This digital tri- state output is managed by AGC hardware logic to drive external circuitry when input signal attenuation is needed Output — VDDIO (Note 12) VZC Mains Zero-Cross Detection Signal. This input detects the zero-crossing of the mains voltage Input — VDDIO External Protection Resistor (Note 12, 13) VREFP Internal Reference “Plus” Voltage Analog — VDDIN_AN (Note 14) VREFN Internal Reference “Minus” Voltage Analog — VDDIN_AN (Note 14) VREFC Internal Reference Common-mode Voltage Analog — VDDIN_AN (Note 15) |
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