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MPL460AT-I/4LB bảng dữ liệu(PDF) 31 Page - Microchip Technology |
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MPL460AT-I/4LB bảng dữ liệu(HTML) 31 Page - Microchip Technology |
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31 / 48 page ![]() PL460 Reception Path Data Sheet © 2020-2023 Microchip Technology Inc. and its subsidiaries DS60001666D - 31 10. Reception Path The PL460 modem has a single-ended reception stage as it is shown in the figure below. It supports a maximum input of 24Vpp without saturation. The signal is adapted to the requirements of the Rx path by means of an Automatic Gain Control (AGC) and a Programmable Gain Amplifier (PGA) as it is described in PLC Signal Adaptation. Additionally, the reception stage is also capable to detect zero-crosses (in case of being connected to an AC line) if an adapted signal is provided, as it is explained in Zero-Crossing Detection. Figure 10-1. PL460 Reception Path Block Diagram 10.1. Functional Description 10.1.1. PLC Signal Adaptation The reception path implements several stages to adapt the received signal to avoid saturation of the Analog-to-Digital Converter (ADC) and maximize the dynamic range. The AGC stage uses an external resistor to attenuate the input signal if needed. The PL460 provides a control signal to configure the resistor dynamically in function of the level of signal measured. The PL460 also implements a PGA that adds five levels of gain to adjust the input signal to the ADC. Finally, the DC blocker module is capable to detect and subtract any DC offset to prevent it from affecting the signal processing of the obtained samples. 10.1.2. Zero-Crossing Detection The PL460 implements a zero-crossing detection stage. An external circuit is required to adapt the AC signal to VZC input requirements of the PL460. Once adapted, the zero-crossing detection stage measures rising and falling edges by hardware and then a PLL software algorithm is applied. The center of the low-level pulse input must be aligned with the peak of the mains wave, although some adjustment can be made on the application to correct the delay between pulse and wave as shown in the figure below. |
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