DM505LRBABF datasheet(116/295 Pages) TI2

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116

DM505

SPRS976E – NOVEMBER 2016 – REVISED MAY 2018

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Specifications

5.9.4.3.2 DLL Characteristics

Table 5-27 summarizes the DLL characteristics and assumes testing over recommended operating

conditions.

Table 5-27. DLL Characteristics

NAME

DESCRIPTION

MIN

TYP

MAX

UNIT

finput

Input clock frequency (EMIF_DLL_FCLK)

266

MHz

tlock

Lock time

50k

cycles

trelock

Relock time (a change of the DLL frequency implies that DLL must relock)

50k

cycles

5.9.4.3.2.1 DPLL and DLL Noise Isolation

NOTE

For more information on DPLL and DLL decoupling capacitor requirements, see the External

Capacitors / Voltage Decoupling Capacitors / I/O and Analog Voltage Decoupling / VDDA

Power Domain section.

5.9.5

Recommended Clock and Control Signal Transition Behavior

All clocks and control signals must transition between VIH and VIL (or between VIL and VIH) in a monotonic

manner. Monotonic transitions are more easily guaranteed with faster switching signals. Slower input

transitions are more susceptible to glitches due to noise and special care should be taken for slow input

clocks.

5.9.6

Peripherals

5.9.6.1

Timing Test Conditions

All timing requirements and switching characteristics are valid over the recommended operating conditions

unless otherwise specified.

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