DM505LRBABF datasheet(4/295 Pages) TI2

4 / 295 page

DM505

SPRS976E – NOVEMBER 2016 – REVISED MAY 2018

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Table of Contents

Device Overview

......................................... 1

1.1

Features

............................................. 1

1.2

Applications

........................................... 2

1.3

Description

............................................ 2

1.4

Functional Block Diagram

........................... 3

Revision History

......................................... 5

Device Comparison

..................................... 6

3.1

Device Comparison Table

............................ 6

Terminal Configuration and Functions

.............. 8

4.1

Pin Diagram

.......................................... 8

4.2

Pin Attributes

......................................... 8

4.3

Signal Descriptions

.................................. 38

4.4

Pin Multiplexing

..................................... 64

4.5

Connections for Unused Pins

....................... 75

Specifications

........................................... 76

5.1

Absolute Maximum Ratings

......................... 77

5.2

ESD Ratings

........................................ 77

5.3

Power on Hour (POH) Limits

........................ 77

5.4

Recommended Operating Conditions

............... 79

5.5

Operating Performance Points

...................... 81

5.6

Power Consumption Summary

...................... 90

5.7

Electrical Characteristics

............................ 90

5.8

Thermal Characteristics

............................. 97

5.9

Timing Requirements and Switching

Characteristics

....................................... 98

Detailed Description

.................................. 180

6.1

Description

......................................... 180

6.2

Functional Block Diagram

......................... 180

6.3

DSP Subsystem

................................... 181

6.4

IPU

................................................. 186

6.5

EVE

................................................ 187

6.6

Memory Subsystem

................................ 189

6.7

Interprocessor Communication

.................... 192

6.8

Interrupt Controller

................................. 193

6.9

EDMA

.............................................. 193

6.10

Peripherals

......................................... 195

6.11

On-Chip Debug

.................................... 207

Applications, Implementation, and Layout

...... 211

7.1

Introduction

........................................ 211

7.2

Power Optimizations

............................... 212

7.3

Core Power Domains

.............................. 223

7.4

Single-Ended Interfaces

........................... 233

7.5

Differential Interfaces

.............................. 235

7.6

Clock Routing Guidelines

.......................... 237

7.7

LPDDR2 Board Design and Layout Guidelines

.... 238

7.8

DDR2 Board Design and Layout Guidelines

....... 247

7.9

DDR3 Board Design and Layout Guidelines

....... 259

7.10

CVIDEO/SD-DAC Guidelines and Electrical

Data/Timing

........................................ 282

Device and Documentation Support

.............. 284

8.1

Device Nomenclature

.............................. 284

8.2

Tools and Software

................................ 286

8.3

Documentation Support

............................ 286

8.4

Receiving Notification of Documentation Updates

. 287

8.5

Community Resources

............................. 287

8.6

Trademarks

........................................ 287

8.7

Electrostatic Discharge Caution

................... 288

8.8

Export Control Notice

.............................. 288

8.9

Glossary

............................................ 288

Mechanical Packaging Information

............... 289

9.1

Mechanical Data

................................... 290

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