DM505LRBABF datasheet(99/295 Pages) TI2

99 / 295 page

= V

MAX (or V

MAX)

ref

= V

MIN (or V

MIN)

ref

pm_transvolt_prs403

Vref

pm_io_volt_prs403

Transmission Line

4.0 pF

1.85 pF

Z0 = 50

(see Note)

Tester Pin Electronics

Data Sheet Timing Reference Point

Output

Under

Test

NOTE: The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must be

taken into account. A transmission line with a delay of 2 ns can be used to produce the desired transmission line effect. The transmission line is

intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns) from the data sheet timings.

Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.

42 Ω

3.5 nH

Device Pin

(see Note)

pm_tstcirc_prs403

DM505

www.ti.com

SPRS976E – NOVEMBER 2016 – REVISED MAY 2018

Submit Documentation Feedback

Specifications

5.9.1.1

Parameter Information

Figure 5-1. Test Load Circuit for AC Timing Measurements

The load capacitance value stated is only for characterization and measurement of AC timing signals.

This load capacitance value does not indicate the maximum load the device is capable of driving.

5.9.1.1.1 1.8V and 3.3V Signal Transition Levels

All input and output timing parameters are referenced to Vref for both "0" and "1" logic levels. Vref = (VDD

I/O)/2.

Figure 5-2. Input and Output Voltage Reference Levels for AC Timing Measurements

All rise and fall transition timing parameters are referenced to VIL MAX and VIH MIN for input clocks, VOL

MAX and VOH MIN for output clocks.

Figure 5-3. Rise and Fall Transition Time Voltage Reference Levels

5.9.1.1.2 1.8V and 3.3V Signal Transition Rates

The default SLEWCONTROL settings in each pad configuration register must be used to guaranteed

timings, unless specific instructions otherwise are given in the individual timing sub-sections of the

datasheet.

All timings are tested with an input edge rate of 4 volts per nanosecond (4 V/ns).

DM505LRBABF bảng dữ liệu(PDF) 99 Page - Texas Instruments

DM505LRBABF bảng dữ liệu(HTML) 99 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL