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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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DM505LRBABF bảng dữ liệu(PDF) 60 Page - Texas Instruments |
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DM505LRBABF bảng dữ liệu(HTML) 60 Page - Texas Instruments |
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60 / 295 page  60 DM505 SPRS976E – NOVEMBER 2016 – REVISED MAY 2018 www.ti.com Submit Documentation Feedback Terminal Configuration and Functions Copyright © 2016–2018, Texas Instruments Incorporated Table 4-23. Sysboot Signal Descriptions SIGNAL NAME DESCRIPTION TYPE BALL sysboot0 Boot Mode Configuration 0. The value latched on this pin upon porz reset release will determine the boot mode configuration of the device. I E8 sysboot1 Boot Mode Configuration 1. The value latched on this pin upon porz reset release will determine the boot mode configuration of the device. I A7 sysboot2 Boot Mode Configuration 2. The value latched on this pin upon porz reset release will determine the boot mode configuration of the device. I F8 sysboot3 Boot Mode Configuration 3. The value latched on this pin upon porz reset release will determine the boot mode configuration of the device. I B7 sysboot4 Boot Mode Configuration 4. The value latched on this pin upon porz reset release will determine the boot mode configuration of the device. I A6 sysboot5 Boot Mode Configuration 5. The value latched on this pin upon porz reset release will determine the boot mode configuration of the device. I F7 sysboot6 Boot Mode Configuration 6. The value latched on this pin upon porz reset release will determine the boot mode configuration of the device. I E7 sysboot7 Boot Mode Configuration 7. The value latched on this pin upon porz reset release will determine the boot mode configuration of the device. I R7 sysboot8 Boot Mode Configuration 8. The value latched on this pin upon porz reset release will determine the boot mode configuration of the device. I B6 sysboot9 Boot Mode Configuration 9. The value latched on this pin upon porz reset release will determine the boot mode configuration of the device. I A5 sysboot10 Boot Mode Configuration 10. The value latched on this pin upon porz reset release will determine the boot mode configuration of the device. I D6 sysboot11 Boot Mode Configuration 11. The value latched on this pin upon porz reset release will determine the boot mode configuration of the device. I C5 sysboot12 Boot Mode Configuration 12. The value latched on this pin upon porz reset release will determine the boot mode configuration of the device. I B5 sysboot13 Boot Mode Configuration 13. The value latched on this pin upon porz reset release will determine the boot mode configuration of the device. I D7 sysboot14 Boot Mode Configuration 14. The value latched on this pin upon porz reset release will determine the boot mode configuration of the device. I B4 sysboot15 Boot Mode Configuration 15. The value latched on this pin upon porz reset release will determine the boot mode configuration of the device. I A4 4.3.22.2 Power, Reset and Clock Management (PRCM) NOTE For more information, see Power, Reset, and Clock Management section of the Device TRM. Table 4-24. PRCM Signal Descriptions SIGNAL NAME DESCRIPTION TYPE BALL clkout0 Device Clock output 1. Can be used externally for devices with non-critical timing requirements, or for debug, or as a reference clock on GPMC as described in Table 5-34, GPMC/NOR Flash Interface Switching Characteristics - Synchronous Mode - 1 Load and Table 5-36, GPMC/NOR Flash Interface Switching Characteristics - Synchronous Mode - 5 Loads. O AB17, C12, F14, F22, M1 clkout1 Device Clock output 2. Can be used as a system clock for other devices. O F12, F21, U17 clkout2 Device Clock output 3. Can be used as a system clock for other devices. O A10, F20, W17 rstoutn Reset out (Active low). This pin asserts low in response to any global reset condition on the device. O F4 resetn Device Reset Input I G4 porz Power on Reset (active low). This pin must be asserted low until all device supplies are valid (see reset sequence/requirements). I G3 xref_clk0 External Reference Clock 0. For Audio and other Peripherals. I M1 |
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