DM505LRBABF datasheet(113/295 Pages) TI2

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DM505

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SPRS976E – NOVEMBER 2016 – REVISED MAY 2018

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Specifications

•

clkout3 - Device Clock output 3. Can be used as a system clock for other devices. The source of the

clkout3 could be either:

–

The input system clock and alternate clock (xi_osc0 or xi_osc1)

–

CORE clock (from CORE output)

–

192-MHz clock (from PER DPLL output)

For more information about Output Clocks see Device TRM, Chapter: Power, Reset, and Clock

Management.

5.9.4.3

DPLLs, DLLs

NOTE

For more information, see:

•

Power, Reset, and Clock Management / Clock Management Functional Description /

Internal Clock Sources / Generators / Generic DPLL Overview Section

and

•

Display Subsystem / Display Subsystem Overview section of the Device TRM.

To generate high-frequency clocks, the device supports multiple on-chip DPLLs controlled directly by the

PRCM module.

•

They have their own independent power domain (each one embeds its own switch and can be

controlled as an independent functional power domain)

•

They are fed with ALWAYS ON system clock, with independent control per DPLL.

The different DPLLs managed by the PRCM are listed below:

•

DPLL_CORE: It supplies all interface clocks and also few module functional clocks.

•

DPLL_PER: It supplies several clock sources: a 192-MHz clock for the display functional clock , a

96-MHz functional clock to subsystems and peripherals.

•

DPLL_GMAC_DSP: It supplies RGMII, EVE1 and DSP0 module functional clocks.

•

DPLL_EVE_VID_DSP: It provides a few module functional clocks (EVE_GFCLK, VID_PIX_CLK

and DSP1_CLK).

•

DPLL_DDR: It generates clocks for the one External Memory Interface (EMIF) controller and its

associated EMIF PHYs.

NOTE

The following DPLLs are controlled by the clock manager located in the always-on Core

power domain (CM_CORE_AON):

•

DPLL_CORE, DPLL_DDR, DPLL_GMAC_DSP, DPLL_PER, DPLL_EVE_VID_DSP.

For more information on CM_CORE_AON and CM_CORE or PRCM DPLLs, see the Power, Reset, and

Clock Management (PRCM) chapter of the Device TRM.

5.9.4.3.1 DPLL Characteristics

The DPLL has three relevant input clocks. One of them is the reference clock (CLKINP) used to generated

the synthesized clock but can also be used as the bypass clock whenever the DPLL enters a bypass

mode. It is therefore mandatory. The second one is a fast bypass clock (CLKINPULOW) used when

selected as the bypass clock and is optional. The third clock (CLKINPHIF) is explained in the next

paragraph.

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