DM505LRBABF datasheet(114/295 Pages) TI2

tên linh kiện	DM505LRBABF

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114

DM505

SPRS976E – NOVEMBER 2016 – REVISED MAY 2018

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Specifications

The DPLL has three output clocks (namely CLKOUT, CLKOUTX2, and CLKOUTHIF). CLKOUT and

CLKOUTX2 run at the bypass frequency whenever the DPLL enters a bypass mode. Both of them are

generated from the lock frequency divided by a post-divider (namely M2 post-divider). The third clock,

CLKOUTHIF, has no automatic bypass capability. It is an output of a post-divider (M3 post-divider) with

the input clock selectable between the internal lock clock (Fdpll) and CLKINPHIF input of the PLL through

an asynchronous multplexing.

For more information, see the Power, Reset, and Clock Management chapter of the Device TRM.

Table 5-25 summarizes DPLL type described in Section 5.9.4.3, DPLLs, DLLs Specifications.

Table 5-25. DPLL Control

DPLL NAME

CONTROLLED BY PRCM

DPLL_CORE

Yes(1)

DPLL_EVE_VID_DSP

Yes(1)

DPLL_GMAC_DSP

Yes(1)

DPLL_PER

Yes(1)

DPLL_DDR

Yes(1)

(1) DPLL is in the always-on domain.

Table 5-26 and summarize the DPLL characteristics and assume testing over recommended operating

conditions.

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