DM505LRBABF datasheet(120/295 Pages) TI2

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vouti_clk

vouti_vsync

vouti_hsync

vouti_d[23:0]

vouti_de

vouti_fld

data_1 data_2

data_n

odd

even

SWPS049-018

vouti_clk

Falling-edge Clock Reference

Rising-edge Clock Reference

120

DM505

SPRS976E – NOVEMBER 2016 – REVISED MAY 2018

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Specifications

CAUTION

All pads/balls configured as vouti_* signals must be programmed to use slow

slew rate by setting the corresponding CTRL_CORE_PAD_*[SLEWCONTROL]

Table 5-31 and Figure 5-21 assume testing over the recommended operating conditions and electrical

characteristic conditions.

Table 5-31. DPI Video Output 1 Switching Characteristics(1)(2)

NO.

PARAMETER

DESCRIPTION

MODE

MIN

MAX

UNIT

tc(clk)

Cycle time, output pixel clock vouti_clk

6.73

tw(clkL)

Pulse duration, output pixel clock vouti_clk low

P×0.5-1

tw(clkH)

Pulse duration, output pixel clock vouti_clk high

P×0.5-1

td(clk-ctlV)

Delay time, output pixel clock vouti_clk transition to output

data vouti_d[23:0] valid

DPI1

-1.33

1.01

td(clk-dV)

Delay time, output pixel clock vouti_clk transition to output

control signals vouti_vsync, vouti_hsync, vouti_de, and

vouti_fld valid

DPI1

-1.33

1.01

(1) P = output vout1_clk period in ns.

(2) All pads/balls configured as vouti_* signals must be programmed to use slow slew rate by setting the corresponding

CTRL_CORE_PAD_*[SLEWCONTROL] register field to SLOW (0b1).

(3) SERDES transceivers may be sensitive to the jitter profile of vouti_clk. See Application Note SPRAC62 for additional guidance.

Figure 5-21. DPI Video Output(1)(2)(3)

(1) The configuration of assertion of the data can be programmed on the falling or rising edge of the pixel clock.

(2) The polarity and the pulse width of vout1_hsync and vout1_vsync are programmable, refer to the DSS section of the device TRM.

(3) The vout1_clk frequency can be configured, refer to the DSS section of the device TRM.

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