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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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TMPR4937 bảng dữ liệu(PDF) 277 Page - Toshiba Semiconductor |
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TMPR4937 bảng dữ liệu(HTML) 277 Page - Toshiba Semiconductor |
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277 / 552 page  Chapter 10 PCI Controller 10-19 10.3.11.2 PDMAC Interrupts Name Status Bit Interrupt Enable Bit Normal Chain Termination NCCMP NCCMPIE Normal Data Transfer Termination NTCMP NTCMPIE Inter-Transfer Stall Time Reached STLTRF Configuration Error CFGERR PCI Fatal Error PCIERR G-Bus Chain Error CHNERR G-Bus Data Error PDMSTATUS DATAERR PDMCFG ERRIE 10.3.11.3 Power Management Interrupts Name Status Bit Interrupt Enable Bit PM Status Change Detect PMSC PMSCIE PME_En Set Detect PMEES PMEESIE PME Status Clear Detect P2GSTATUS PMECLR P2GMASK PMECLRIE PME Detect PCICSTATUS PME PCICMASK PMEIE 10.3.11.4 Error Detection Interrupts Name Status Bit Interrupt Enable Bit Parity Error Detect DPE DPEIE System Error Report SSE SSEIE Master Abort Receive RMA RMAIE Target Abort Receive RTA RTAIE Target Abort Report STA STAIE Master Data Parity Error PCISTATUS / PCISSTATUS MDPE PCIMASK MDPEIE TRDY Timeout Error IDTTOE IDTTOEIE Retry Timeout Error G2PSTATUS IDRTOE G2PMASK IDRTOEIE Broken Master Detect PBASTATUS BMD PBAMASK BMDIE Long Burst Transfer Detect TLB TLBIE Negative Increase Burst Transfer Detect NIB NIBIE Zero Increase Burst Transfer Detect ZIB ZIBIE PERR* Detect PERR PERRIE SERR* Detect SERR SERRIE G-Bus Bus Error Detect PCICSTATUS GBE PCICMASK GBEIE Note: In the initiator write cycle, access on the G-Bus has been finished before access on the PCI bus is finished (Post write). Therefore, when an error occurs on PCI bus, it is reported with an error detection interrupt, as shown above. In the initiator read cycle, when an error occurs on the PCI bus access, PCIC responds with a G-Bus error instead of returning read data to the G-Bus. Setting "0" to the IRBER bit of the PCICFG register suppresses output of a G-Bus error during initiator read. |
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