TMPR4937 datasheet(98/552 Pages) TOSHIBA

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Chapter 6 Clocks

6-4

Table 6.1.2 Relationship Among Different Clock Frequencies (for TMPR4937XBG-300, CPUCLK = 266 MHz)

Master Clock (Input)

and Boot Configured

Settings

Internal Clock

External Clock (Output)

SYSCLK (MHz)

PCICLK[5:0] (MHz) †

Boot Configured Settings

PCIDIVMODE[2:0]

CCFG Settings

PCIDIVMODE[2:0]

MASTERCLK

(MHz)

Boot

Configured

Setting

ADDR[3:0]

CPUCLK

(MHz)

GBUSCLK

(MHz)

IMBUSCLK

(MHz)

SDCLK

[3:0]

(MHz)

(1/1)

(1/2)

(1/3)

(1/4)

LLH

(1/4)

LHH

(1/4.5)

HLH

(1/5)

HHH

(1/5.5)

LLL

(1/8)

LHL

(1/9)

HLL

(1/10)

HHL

(1/11)

133

HHHH (×2.0)

33.3

HLHH (×8.0)

133

66 44.3 33.3

106.4

HHHL (×2.5)

26.6

HLHL (×10.0)

106.4

106.4 106.4

53 35.5 26.6

88.7

HHLH (×3.0)

22.2

HLLH (×12.0)

88.7

44.3 29.6 22.2

66.5

HHLL (×4.0)

16.6

HLLL (×16.0)

66.5

33.2

66.5

33.3 22.2 16.6

59.1

LHHH (×4.5)

14.8

LLHH (×18.0)

266

59.1

29.6

59.1

29.6 19.7 14.8

66.5

59.1

53.2

48.4

33.3 29.6 26.6 24.2

† The CCFG.PCIDIVMODE[2:1] field is setting by the boot configuration ADDR[11:10].

Table 6.1.3 Relationship Among Different Clock Frequencies (for TMPR4937XBG-300, CPUCLK = 300 MHz)

Master Clock (Input)

and Boot Configured

Settings

Internal Clock

External Clock (Output)

SYSCLK (MHz)

PCICLK[5:0] (MHz) †

Boot Configured Settings

PCIDIVMODE[2:0]

CCFG Settings

PCIDIVMODE[2:0]

MASTERCLK

(MHz)

Boot

Configured

Setting

ADDR[3:0]

CPUCLK

(MHz)

GBUSCLK

(MHz)

IMBUSCLK

(MHz)

SDCLK

[3:0]

(MHz)

(1/1)

(1/2)

(1/3)

(1/4)

LLH

(1/4)

LHH

(1/4.5)

HLH

(1/5)

HHH

(1/5.5)

LLL

(1/8)

LHL

(1/9)

HLL

(1/10)

HHL

(1/11)

HHHH(x2.0)

HLHH(x8.0)

120

HHHL (x2.5)

HLHL (x10.0)

120

100

HHLH (x3.0)

HLLH (x12.0)

100

HHLL (x4.0)

HLLL (x16.0)

LHHH(x4.5)

LLHH (x18.0)

300

† The CCFG.PCIDIVMODE[2:1] field is setting by the boot configuration ADDR[11:10].

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