TMPR4937 datasheet(47/552 Pages) TOSHIBA

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Chapter 1 Overview and Features

1-1

Overview and Features

1.1

Overview

The TMPR4937 (TX4937) is a standard microcontroller that belongs to the 64-bit TX System RISC TX49

family.

The TX4937 uses the TX49/H3 core as its CPU. The TX49/H3 core is a 64-bit RISC core that Toshiba

developed based on the MIPS III architecture of MIPS Technologies, Inc. (MIPS). For details of the

TX49/H3 core such as instruction sets, see “64-bit TX System RISC TX49/H2, TX49/H3, TX49/H4 Core

Architecture”.

In addition to the TX49/H3 core, the TX4937 uses as microcontrollers for embedded applications an

External Bus Controller, DMA Controllers, SDRAM Controller, PCI Controller. The TX4937 also has

peripheral circuits such as a serial I/O port, a timer/counter, a parallel I/O port, an AC-link Controller and an

Interrupt Controller. By having an on-chip a data bus with a maximum width of 64 bits and an SDRAM

Controller with a memory clock frequency of 133 MHz, the TX4937 realizes low memory access latency and

high memory bandwidth. This allows the TX4937 to show its capacity as a high-performance CPU core.

1.2

Features

•

TX49/H3 core

Maximum Operating Frequency: 300 MHz (TMPR4937XBG-300), 333 MHz (TMPR4937XBG-333)

On-chip IEEE754-compliant single/double precision floating point unit (FPU) function

•

External Bus Controller (8 channels)

•

DMA (Direct Memory Access) Controllers (8 channels)

•

SDRAM Controller (4 channels)

64-bit Data Bus

Memory Clock Frequency: 133 MHz (For relationship between CPU clock and memory clock, see

Section 6.1)

Supports ECC/Parity

•

PCI Controller

Complies with PCI Local Bus Specification Revision 2.2

PCI Bus Clock Frequency: 66 MHz/33 MHz

•

Serial I/O Port (2 channels)

•

Timer/Counter (3 channels)

•

Parallel I/O Port (Maximum 16 bits)

•

AC-link Controller

•

Interrupt Controller

•

Selectable Little Endian mode or Big Endian mode

•

Low Power Consumption

Supports internal 1.5 V, IO block 3.3 V operation, and low power consumption mode (Halt)

•

Supports IEEE1149.1 (JTAG): Debugging Support Unit (EJTAG)

•

Package: 484-pin PBGA (with 64pin thermal ball)

(There is pin compatible nature with TX4927 except thermal balls.)

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