TMPR4937 datasheet(269/552 Pages) TOSHIBA

269 / 552 page

Chapter 10 PCI Controller

10-11

When expressed as a formula, conversion of a PCI Bus Address (PCIAddr[39:0]) into a G-Bus

address (GBusAddr[35:0]) is as follows below. GBASE[35:8], and PBASE[39:8] each represent the

setting register of the corresponding access window indicated below in Table 10.3.4. The “&” symbol

indicates a logical AND for each bit, and “|” indicates bit linking.

Memory space 0

If (PCIAddr[39:29] == P2GM0PUBASE.BA[39:32] | P2GM0PLBASE.BA[31:29] then

GBusAddr[35:0] = P2GM0GBASE[35:29] | PCIAddr[28:0];

Memory space 1

If (PCIAddr[39:24] == P2GM1PUBASE.BA[39:32] | P2GM1PLBASE.BA[31:24] then

GBusAddr[35:0] = P2GM1GBASE[35:24] | PCIAddr[23:0];

Memory space 2

If (PCIAddr[31:20] == P2GM2PBASE.BA[31:20]) then

GBusAddr[35:0] = P2GM2GBASE[35:20] | PCIAddr[19:0];

I/O space

If (PCIAddr[31:8] == P2GIOPBASE.BA[31:8]) then

GBusAddr[35:0] = P2GIOGBASE[35:8] | PCIAddr[7:0];

Table 10.3.4 Target Access Space Address Mapping Register

Space

Size

PCI

Address

PCI Bus Base Address PBASE

G-Bus Base Address

GBASE

Memory Space 0 512 MB

40-bit

P2GM0PUBASE.BA[39:32] | P2GM0PLBASE.BA[31:29]

P2GM0GBASE.BA[35:29]

Memory Space 1 16 MB

40-bit

P2GM1PUBASE.BA[39:32] | P2GM1PLBASE.BA[31:24]

P2GM1GBASE.BA[35:24]

Memory Space 2 1 MB

32-bit

P2GM2PBASE.BA[31:20]

P2GM2GBASE.BA[35:20]

I/O Space

256 B

32-bit

P2GIOPBASE.BA[31:8]

P2GIOGBASE.BA[35:8]

Figure 10.3.6 illustrates this address conversion.

= 29 Memory Space 0

= 24 Memory Space 1

= 20 Memory Space 2

= 8 I/O Space

Figure 10.3.6 Address Conversion for Target (PCI Bus (PCI Bus → G-Bus Address Conversion)

Compare

GBASE

GBusAddr

39/32

PCIAddr

−1

39/32

n n

−1

n n

−1

PBASE

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